SR 

         Status Register.
This is a read-only register used to indicate the current transfer status,
FIFO status, and any transmission/reception errors that may have occurred.
The status register may be read at any time. None of the bits in this
register request an interrupt.
Module Instance Base Address Register Address
i_spim_0_ssi_address_block 0xFFDA4000 0xFFDA4028
i_spim_1_ssi_address_block 0xFFDA5000 0xFFDA5028

Size: 32

Offset: 0x28

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_SR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_SR

RO 0x0

DCOL

RO 0x0

RSVD_TXE

RO 0x0

RFF

RO 0x0

RFNE

RO 0x0

TFE

RO 0x1

TFNF

RO 0x1

BUSY

RO 0x0

SR Fields

Bit Name Description Access Reset
31:7 RSVD_SR 
Reserved bits - Read Only
 RO 0x0
6 DCOL 
Data Collision Error.
Relevant only when the DW_apb_ssi is configured as a master device.
This bit will be set if ss_in_n input is asserted by other master,
when the DW_apb_ssi master is in the middle of the transfer. This informs the processor that the
last data transfer was halted before completion. This bit is cleared
when read.

0 - No error

1 - Transmit data collision error
Value Description
0x0 No Data Error Condition
0x1 TX Data Collision Error
RO 0x0
5 RSVD_TXE 
Reserved field- read-only
 RO 0x0
4 RFF 
Receive FIFO Full. When the receive FIFO is completely full, this bit
is set. When the receive FIFO contains one or more empty location, this
bit is cleared.

0 - Receive FIFO is not full

1 - Receive FIFO is full
Value Description
0x0 RX FIFO is not full
0x1 Rx FIFO is full
RO 0x0
3 RFNE 
Receive FIFO Not Empty.
Set when the receive FIFO contains one or more entries and is cleared
when the receive FIFO is empty. This bit can be polled by software to
completely empty the receive FIFO.

0 - Receive FIFO is empty

1 - Receive FIFO is not empty
Value Description
0x0 Rx FIFO is empty
0x1 Rx FIFO is nonempty
RO 0x0
2 TFE 
Transmit FIFO Empty.
When the transmit FIFO is completely empty, this bit is set. When the
transmit FIFO contains one or more valid entries, this bit is cleared.
This bit field does not request an interrupt.

0 - Transmit FIFO is not empty

1 - Transmit FIFO is empty
Value Description
0x0 Tx FIFO is nonempty
0x1 Tx FIFO is empty
RO 0x1
1 TFNF 
Transmit FIFO Not Full. Set when the transmit FIFO contains one or more
empty locations, and is cleared when the FIFO is full.

0 - Transmit FIFO is full

1 - Transmit FIFO is not full
Value Description
0x0 Tx FIFO is full
0x1 Tx FIFO is not Full
RO 0x1
0 BUSY 
SSI Busy Flag.
When set, indicates that a serial transfer is in progress; when cleared
indicates that the DW_apb_ssi is idle or disabled.

0 - DW_apb_ssi is idle or disabled

1 - DW_apb_ssi is actively transferring data
Value Description
0x0 SSI is Idle/Disabled
0x1 SSI is Active
RO 0x0