reg_ctrlcfg2
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010030

Size: 32

Offset: 0x30

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_dbc3_pipe_lat

RW 0x0

cfg_dbc2_pipe_lat

RW 0x0

cfg_dbc1_pipe_lat

RW 0x0

cfg_dbc0_pipe_lat

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc0_pipe_lat

RW 0x0

cfg_dbc2ctrl_sel

RW 0x0

cfg_dbc3_ctrl_sel

RW 0x0

cfg_dbc2_ctrl_sel

RW 0x0

cfg_dbc1_ctrl_sel

RW 0x0

cfg_dbc0_ctrl_sel

RW 0x0

cfg_ctrl2dbc_switch1

RW 0x0

cfg_ctrl2dbc_switch0

RW 0x0

cfg_dbc3_output_regd

RW 0x0

cfg_dbc2_output_regd

RW 0x0

cfg_dbc1_output_regd

RW 0x0

cfg_dbc0_output_regd

RW 0x0

cfg_ctrl_output_regd

RW 0x0

reg_ctrlcfg2 Fields

Bit Name Description Access Reset
26:24 cfg_dbc3_pipe_lat 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_pipe_lat[2:0]
Name:DBC3 – pipeline latency
Description:Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC3.
RW 0x0
23:21 cfg_dbc2_pipe_lat 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_pipe_lat[2:0]
Name:DBC2 – pipeline latency
Description:Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC2.
RW 0x0
20:18 cfg_dbc1_pipe_lat 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_pipe_lat[2:0]
Name:DBC1 – pipeline latency
Description:Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC1.
RW 0x0
17:15 cfg_dbc0_pipe_lat 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_pipe_lat[2:0]
Name:DBC0 – pipeline latency
Description:Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC0.
RW 0x0
14:13 cfg_dbc2ctrl_sel 
iohmc_ctrl_mmr_top_inst.cfg_dbc2ctrl_sel[1:0]
Name:Control path-DBC select
Description:Specifies which DBC is driven by the local control path. 2’b00: DBC0; 2’b01: DBC1; 2’b10: DBC2; 2’b11: DBC3.
RW 0x0
12 cfg_dbc3_ctrl_sel 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_ctrl_sel
Name:DBC3 – control path select
Description:DBC3 – control path select. 1’b0: The upper MUX in io_hmc_dbc_switch is selected; 1’b1: The lower mux is selected.
RW 0x0
11 cfg_dbc2_ctrl_sel 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_ctrl_sel
Name:DBC2 – control path select
Description:DBC2 – control path select. 1’b0: The upper MUX in io_hmc_dbc_switch is selected; 1’b1: The lower mux is selected.
RW 0x0
10 cfg_dbc1_ctrl_sel 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_ctrl_sel
Name:DBC1 – control path select
Description:DBC1 – control path select. 1’b0: The upper MUX in io_hmc_dbc_switch is selected; 1’b1: The lower mux is selected.
RW 0x0
9 cfg_dbc0_ctrl_sel 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_ctrl_sel
Name:DBC0 – control path select
Description:DBC0 – control path select. 1’b0: The upper MUX in io_hmc_dbc_switch is selected; 1’b1: The lower mux is selected.
RW 0x0
8:7 cfg_ctrl2dbc_switch1 
iohmc_ctrl_mmr_top_inst.cfg_ctrl2dbc_switch1[1:0]
Name:Control source switch1 select
Description:Select of the MUX ctrl2dbc_switch1. 2’b00 – selects the control path from upper tiles.  2’b01 – selects the local control path. 2’b10 – selects the control path from lower tiles. 2’b11 – illegal selection.
RW 0x0
6:5 cfg_ctrl2dbc_switch0 
iohmc_ctrl_mmr_top_inst.cfg_ctrl2dbc_switch0[1:0]
Name:Control source switch0 select
Description:Select of the MUX ctrl2dbc_switch0. 2’b00 – selects the control path from upper tiles.  2’b01 – selects the local control path. 2’b10 – selects the control path from lower tiles. 2’b11 – illegal selection.
RW 0x0
4 cfg_dbc3_output_regd 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_output_regd
Name:Reserved
Description:TBD
RW 0x0
3 cfg_dbc2_output_regd 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_output_regd
Name:Reserved
Description:TBD
RW 0x0
2 cfg_dbc1_output_regd 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_output_regd
Name:Reserved
Description:TBD
RW 0x0
1 cfg_dbc0_output_regd 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_output_regd
Name:Reserved
Description:TBD
RW 0x0
0 cfg_ctrl_output_regd 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_output_regd
Name:Reserved
Description:TBD
RW 0x0