fhop 

         Frequency Hopping (FHOP)/Dynamic Frequency Scaling(DFS) Control and status register.
Module Instance Base Address Register Address
i_clk_mgr_perpllgrp 0xFFD1007C 0xFFD100C4

Size: 32

Offset: 0x48

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

ack

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

req

RW 0x0

Reserved

dir

RW 0x0

fhop Fields

Bit Name Description Access Reset
16 ack 
Asynchronous output. Acknowledge signal for the frequency ramp. 
Indicates that the FHOP request, triggered by asserting ictl_pll_freqgen_hop_req_a, has been completed.
1—Triggered FHOP request has been completed. This signal will remain at 1 until ictl_pll_freqgen_hop_req_a has been set to 0, at which point, this signal will de-assert to 0.
0—Meaning depends on the state of ictl_pll_freqgen_hop_req_a. If req is 1, then 0 implies that requested FHOP is in progress. If req is 0, then 0 implies that no FHOP request is pending.
 RO 0x0
8 req 
Request the HP PLL IP to perform the configured FHOP.
1—Trigger FHOP request. Must be held at 1 until octl_pll_freq_hop_ack_a is asserted, at which point, this signal must be de-asserted to 0.
0—No request. This should be the default state of this pin.
It is an Asynchronous Input.
 RW 0x0
1:0 dir 
One-hot encoded. 
Controls the direction of the FHOP. This pin must be updated at least two reference clock cycles before asserting ictl_pll_freqgen_hop_req_a.
2’b01—FHOP up, that is, the target frequency will be faster than the current frequency.
2’b10—FHOP down, that is, the target frequency will be slower than the current frequency.
Value Description
0x1 FHOP_UP
0x2 FHOP_DOWN
RW 0x0