rb_pin_enabled 

         Interrupt or polling mode. Ready/Busy pin is enabled from device.
Module Instance Base Address Register Address
sdm_i_nand_config 0xFFA10000 0xFFA10060

Size: 32

Offset: 0x60

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

bank3

RW 0x0

bank2

RW 0x0

bank1

RW 0x0

bank0

RW 0x1

rb_pin_enabled Fields

Bit Name Description Access Reset
3 bank3 
Sets Cadence Flash Controller in interrupt pin or polling mode
                                       [list][*]1 - R/B pin enabled for bank 3. Interrupt pin mode. 
                                       [*]0 - R/B pin disabled for bank 3. Polling mode.[/list]
 RW 0x0
2 bank2 
Sets Cadence Flash Controller in interrupt pin or polling mode
                                       [list][*]1 - R/B pin enabled for bank 2. Interrupt pin mode. 
                                       [*]0 - R/B pin disabled for bank 2. Polling mode.[/list]
 RW 0x0
1 bank1 
Sets Cadence Flash Controller in interrupt pin or polling mode
                                       [list][*]1 - R/B pin enabled for bank 1. Interrupt pin mode. 
                                       [*]0 - R/B pin disabled for bank 1. Polling mode.[/list]
 RW 0x0
0 bank0 
Sets Cadence Flash Controller in interrupt pin or polling mode
                                       [list][*]1 - R/B pin enabled for bank 0. Interrupt pin mode. 
                                       [*]0 - R/B pin disabled for bank 0. Polling mode.[/list]
 RW 0x1