DMACR
DMA Control Register.
This register is only valid when DW_apb_ssi is configured with a set of
DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is
not configured for DMA operation, this register will not exist and writing
to the register's address will have no effect; reading from this register
address will return zero. The register is used to enable the DMA
Controller interface operation.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_spis_0_ssi_address_block | 0xFFDA2000 | 0xFFDA204C |
| i_spis_1_ssi_address_block | 0xFFDA3000 | 0xFFDA304C |
Size: 32
Offset: 0x4C
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
RSVD_DMACR RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RSVD_DMACR RO 0x0 |
TDMAE RW 0x0 |
RDMAE RW 0x0 |
|||||||||||||
DMACR Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:2 | RSVD_DMACR |
Reserved bits - Read Only |
RO | 0x0 | ||||||
| 1 | TDMAE |
Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0 = Transmit DMA disabled 1 = Transmit DMA enabled
|
RW | 0x0 | ||||||
| 0 | RDMAE |
Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0 = Receive DMA disabled 1 = Receive DMA enabled
|
RW | 0x0 |