DIEPTSIZ0 

         Device IN Endpoint 0 Transfer Size Register
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB00910
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB40910

Size: 32

Offset: 0x910

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

RO 0x0

PktCnt

RW 0x0

RESERVED1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED1

RO 0x0

XferSize

RW 0x0

DIEPTSIZ0 Fields

Bit Name Description Access Reset
31:21 RESERVED 
RESERVED
 RO 0x0
20:19 PktCnt 
Packet Count (PktCnt)
Indicates the total number of USB packets that constitute the
Transfer Size amount of data For endpoint 0.
In Endpoints : This field is decremented every time a packet (maximum size or
short packet) is read from the TxFIFO.
OUT Endpoints: This field is decremented every time a packet (maximum size or
short packet) is written to the RxFIFO.
 RW 0x0
18:7 RESERVED1 
RESERVED
 RO 0x0
6:0 XferSize 
Transfer Size (XferSize)
This field contains the transfer size in bytes for the current endpoint. The transfer size
(XferSize) = Sum of buffer sizes across all descriptors in the list for the endpoint.
In Buffer DMA, the core only interrupts the application after it has exhausted the transfer
size amount of data. The transfer size can be set to the maximum packet size of the
endpoint, to be interrupted at the end of each packet.
 IN Endpoints: The core decrements this field every time a packet from the external
memory is written to the TxFIFO.
 OUT Endpoints: The core decrements this field every time a packet is read from the
RxFIFO and written to the external memory.
RW 0x0