IC_STATUS 

         Name: I2C Status Register
Size: 21 bits
Address Offset: 0x70
Read/Write Access: Read
This is a read-only register used to indicate the current
transfer status and FIFO status. The status register may be
read at any time. None of the bits in this register request
an interrupt.
When the I2C is disabled by writing 0 in bit 0 of the
IC_ENABLE register:
- Bits 1 and 2 are set to 1
- Bits 3 and 10 are set to 0
When the master or slave state machines goes to idle
and ic_en=0:
- Bits 5 and 6 are set to 0
Module Instance Base Address Register Address
i_i2c_emac_0_DW_apb_i2c_addr_block1 0xFFC02A00 0xFFC02A70
i_i2c_emac_1_DW_apb_i2c_addr_block1 0xFFC02B00 0xFFC02B70
i_i2c_emac_2_DW_apb_i2c_addr_block1 0xFFC02C00 0xFFC02C70

Size: 32

Offset: 0x70

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_STATUS_2

RO 0x0

RSVD_SMBUS_ALERT_STATUS

RO 0x0

RSVD_SMBUS_SUSPEND_STATUS

RO 0x0

RSVD_SMBUS_SLAVE_ADDR_RESOLVED

RO 0x0

RSVD_SMBUS_SLAVE_ADDR_VALID

RO 0x0

RSVD_SMBUS_QUICK_CMD_BIT

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_STATUS_1

RO 0x0

RSVD_SDA_STUCK_NOT_RECOVERED

RO 0x0

RSVD_SLV_HOLD_RX_FIFO_FULL

RO 0x0

RSVD_SLV_HOLD_TX_FIFO_EMPTY

RO 0x0

RSVD_MST_HOLD_RX_FIFO_FULL

RO 0x0

RSVD_MST_HOLD_TX_FIFO_EMPTY

RO 0x0

SLV_ACTIVITY

RO 0x0

MST_ACTIVITY

RO 0x0

RFF

RO 0x0

RFNE

RO 0x0

TFE

RO 0x1

TFNF

RO 0x1

IC_STATUS_ACTIVITY

RO 0x0

IC_STATUS Fields

Bit Name Description Access Reset
31:21 RSVD_IC_STATUS_2 
Reserved bits - Read Only
 RO 0x0
20 RSVD_SMBUS_ALERT_STATUS 
Reserved bits - Read Only
 RO 0x0
19 RSVD_SMBUS_SUSPEND_STATUS 
Reserved bits - Read Only
 RO 0x0
18 RSVD_SMBUS_SLAVE_ADDR_RESOLVED 
Reserved bits - Read Only
 RO 0x0
17 RSVD_SMBUS_SLAVE_ADDR_VALID 
Reserved bits - Read Only
 RO 0x0
16 RSVD_SMBUS_QUICK_CMD_BIT 
Reserved bits - Read Only
 RO 0x0
15:12 RSVD_IC_STATUS_1 
Reserved bits - Read Only
 RO 0x0
11 RSVD_SDA_STUCK_NOT_RECOVERED 
Reserved bits - Read Only
 RO 0x0
10 RSVD_SLV_HOLD_RX_FIFO_FULL 
Reserved bits - Read Only
 RO 0x0
9 RSVD_SLV_HOLD_TX_FIFO_EMPTY 
Reserved bits - Read Only
 RO 0x0
8 RSVD_MST_HOLD_RX_FIFO_FULL 
Reserved bits - Read Only
 RO 0x0
7 RSVD_MST_HOLD_TX_FIFO_EMPTY 
Reserved bits - Read Only
 RO 0x0
6 SLV_ACTIVITY 
Slave FSM Activity Status.
When the Slave Finite State Machine (FSM) is not
in the IDLE state, this bit is set.
0: Slave FSM is in IDLE state so the Slave part of
   DW_apb_i2c is not Active
1: Slave FSM is not in IDLE state so the Slave part
   of DW_apb_i2c is Active
Reset value: 0x0
Value Description
0x0 Slave is idle
0x1 Slave not idle
RO 0x0
5 MST_ACTIVITY 
Master FSM Activity Status.
When the Master Finite State Machine (FSM) is
not in the IDLE state, this bit is set.
0: Master FSM is in IDLE state so the Master part
   of DW_apb_i2c is not Active
1: Master FSM is not in IDLE state so the Master
   part of DW_apb_i2c is Active
Note
IC_STATUS[0]-that is, ACTIVITY bit-is the OR of
SLV_ACTIVITY and MST_ACTIVITY bits.
Reset value: 0x0
Value Description
0x0 Master is idle
0x1 Master not idle
RO 0x0
4 RFF 
Receive FIFO Completely Full.
When the receive FIFO is completely full, this
bit is set. When the receive FIFO contains one
or more empty location, this bit is cleared.
0: Receive FIFO is not full
1: Receive FIFO is full
Reset value: 0x0
Value Description
0x0 Rx FIFO not full
0x1 Rx FIFO is full
RO 0x0
3 RFNE 
Receive FIFO Not Empty.
This bit is set when the receive FIFO contains one or
more entries; it is cleared when the receive FIFO is empty.
0: Receive FIFO is empty
1: Receive FIFO is not empty
Reset value: 0x0
Value Description
0x0 Rx FIFO is empty
0x1 Rx FIFO not empty
RO 0x0
2 TFE 
Transmit FIFO Completely Empty.
When the transmit FIFO is completely empty, this bit is set.
When it contains one or more valid entries, this bit is
cleared. This bit field does not request an interrupt.
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
Reset value: 0x1
Value Description
0x0 Tx FIFO not empty
0x1 Tx FIFO is empty
RO 0x1
1 TFNF 
Transmit FIFO Not Full.
Set when the transmit FIFO contains one or more
empty locations, and is cleared when the FIFO is full.
0: Transmit FIFO is full
1: Transmit FIFO is not full
Reset value: 0x1
Value Description
0x0 Tx FIFO is full
0x1 Tx FIFO not full
RO 0x1
0 IC_STATUS_ACTIVITY 
I2C Activity Status.
Reset value: 0x0
Value Description
0x0 I2C is idle
0x1 I2C is active
RO 0x0