IC_ENABLE_STATUS
Name: I2C Enable Status Register
Size: 3 bits
Address Offset: 0x9C
Read/Write Access: Read
The register is used to report the DW_apb_i2c hardware
status when the IC_ENABLE[0] register is set from 1 to 0;
that is, when DW_apb_i2c is disabled.
If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0,
and bit 0 is forced to 1.
If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid
as soon as bit 0 is read as '0'.
Note
When IC_ENABLE[0] has been written with '0'a delay occurs for
bit 0 to be read as '0' because disabling the DW_apb_i2c
depends on I2C bus activities.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_i2c_emac_0_DW_apb_i2c_addr_block1 | 0xFFC02A00 | 0xFFC02A9C |
| i_i2c_emac_1_DW_apb_i2c_addr_block1 | 0xFFC02B00 | 0xFFC02B9C |
| i_i2c_emac_2_DW_apb_i2c_addr_block1 | 0xFFC02C00 | 0xFFC02C9C |
Size: 32
Offset: 0x9C
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
RSVD_IC_ENABLE_STATUS RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RSVD_IC_ENABLE_STATUS RO 0x0 |
SLV_RX_DATA_LOST RO 0x0 |
SLV_DISABLED_WHILE_BUSY RO 0x0 |
IC_EN RO 0x0 |
||||||||||||
IC_ENABLE_STATUS Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:3 | RSVD_IC_ENABLE_STATUS |
Reserved bits - Read Only |
RO | 0x0 | ||||||
| 2 | SLV_RX_DATA_LOST |
Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0
|
RO | 0x0 | ||||||
| 1 | SLV_DISABLED_WHILE_BUSY |
Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0
|
RO | 0x0 | ||||||
| 0 | IC_EN |
ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, DW_apb_i2c is deemed to be in an enabled state. When read as 0, DW_apb_i2c is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0
|
RO | 0x0 |