IC_RX_TL

         Name: I2C Receive FIFO Threshold Register
Size: 8bits
Address Offset: 0x38
Read/Write Access: Read/Write

Module Instance	Base Address	Register Address
`i_i2c_emac_0_DW_apb_i2c_addr_block1`	`0xFFC02A00`	`0xFFC02A38`
`i_i2c_emac_1_DW_apb_i2c_addr_block1`	`0xFFC02B00`	`0xFFC02B38`
`i_i2c_emac_2_DW_apb_i2c_addr_block1`	`0xFFC02C00`	`0xFFC02C38`

Size: 32

Offset: 0x38

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_IC_RX_TL` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_IC_RX_TL` `RO 0x0`								`RX_TL` `RW 0x0`

IC_RX_TL Fields

Bit	Name	Description	Access	Reset
31:8	`RSVD_IC_RX_TL`	Reserved bits - Read Only	`RO`	`0x0`
7:0	`RX_TL`	Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. Reset value: IC_RX_TL configuration parameter	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:8

RSVD_IC_RX_TL

Reserved bits - Read Only

RO

0x0

7:0

RX_TL

Receive FIFO Threshold Level
Controls the level of entries (or above) that triggers
the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register).
The valid range is 0-255, with the additional restriction that
hardware does not allow this value to be set to a value larger
than the depth of the buffer. If an attempt is made to do that,
the actual value set will be the maximum depth of the buffer.
A value of 0 sets the threshold for 1 entry, and a value of 255
sets the threshold for 256 entries.
Reset value: IC_RX_TL configuration parameter

RW

0x0