IC_SS_SCL_HCNT

         Name: Standard Speed I2C Clock SCL High Count Register
Size: 16 bits
Address Offset: 0x14
Read/Write Access: Read/Write
Dependencies: This register is not applicable  when IC_ULTRA_FAST_MODE=1

Module Instance	Base Address	Register Address
`i_i2c_emac_0_DW_apb_i2c_addr_block1`	`0xFFC02A00`	`0xFFC02A14`
`i_i2c_emac_1_DW_apb_i2c_addr_block1`	`0xFFC02B00`	`0xFFC02B14`
`i_i2c_emac_2_DW_apb_i2c_addr_block1`	`0xFFC02C00`	`0xFFC02C14`

Size: 32

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_IC_SS_SCL_HIGH_COUNT` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`IC_SS_SCL_HCNT` `RW 0x1F4`

IC_SS_SCL_HCNT Fields

Bit	Name	Description	Access	Reset
31:16	`RSVD_IC_SS_SCL_HIGH_COUNT`	Reserved bits - Read Only	`RO`	`0x0`
15:0	`IC_SS_SCL_HCNT`	This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. When the configuration parameter IC_HC_COUNT_VALUES is set to 1, this register is read only. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. Reset value: IC_SS_SCL_HIGH_COUNT configuration parameter	`RW`	`0x1F4`

Bit

Name

Description

Access

Reset

31:16

RSVD_IC_SS_SCL_HIGH_COUNT

Reserved bits - Read Only

RO

0x0

15:0

IC_SS_SCL_HCNT

This register must be set before any I2C bus transaction can take place to
ensure proper I/O timing. This register sets the SCL clock high-period
count for standard speed. 
This register can be written only when the I2C interface is disabled which
corresponds to the IC_ENABLE[0] register being set to 0. Writes at other
times have no effect.
The minimum valid value is 6; hardware prevents values less than this
being written, and if attempted results in 6 being set. For designs with
APB_DATA_WIDTH = 8, the order of programming is important to ensure
the correct operation of the DW_apb_i2c. The lower byte must be
programmed first. Then the upper byte is programmed.
When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
this register is read only.
NOTE: This register must not be programmed to a value higher than
65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle
condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.
Reset value: IC_SS_SCL_HIGH_COUNT configuration parameter

RW

0x1F4