IC_DMA_TDLR

         Name: DMA Transmit Data Level Register
Size: log2(IC_TX_BUFFER_DEPTH)  bits
Address Offset: 0x8c
Read/Write Access: Read/Write
This register is only valid when the DW_apb_i2c
is configured with a set of DMA interface signals
(IC_HAS_DMA = 1). When DW_apb_i2c is not configured
for DMA operation, this register does not exist;
writing to its address has no effect; reading from
its address returns zero.

Module Instance	Base Address	Register Address
`i_i2c_emac_0_DW_apb_i2c_addr_block1`	`0xFFC02A00`	`0xFFC02A8C`
`i_i2c_emac_1_DW_apb_i2c_addr_block1`	`0xFFC02B00`	`0xFFC02B8C`
`i_i2c_emac_2_DW_apb_i2c_addr_block1`	`0xFFC02C00`	`0xFFC02C8C`

Size: 32

Offset: 0x8C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMA_TDLR` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_DMA_TDLR` `RO 0x0`										`DMATDL` `RW 0x0`

IC_DMA_TDLR Fields

Bit	Name	Description	Access	Reset
31:6	`RSVD_DMA_TDLR`	Reserved bits - Read Only	`RO`	`0x0`
5:0	`DMATDL`	Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:6

RSVD_DMA_TDLR

Reserved bits - Read Only

RO

0x0

5:0

DMATDL

Transmit Data Level.
This bit field controls the level at which a
DMA request is made by the transmit logic. It
is equal to the watermark level; that is, the
dma_tx_req signal is generated when the number
of valid data entries in the transmit FIFO is
equal to or below this field value, and TDMAE = 1.
Reset value: 0x0

RW

0x0