CTRL 

         Control register
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_1 0xFF8D1000 0xFF8D1000

Size: 32

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

USE_INTERNAL_DMAC

RW 0x0

ENABLE_OD_PULLUP

RW 0x0

CARD_VOLTAGE_B

RW 0x0

CARD_VOLTAGE_A

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

CEATA_DEVICE_INTERRUPT_STATUS

RW 0x0

SEND_AUTO_STOP_CCSD

RW 0x0

SEND_CCSD

RW 0x0

ABORT_READ_DATA

RW 0x0

SEND_IRQ_RESPONSE

RW 0x0

READ_WAIT

RW 0x0

DMA_ENABLE

RW 0x0

INT_ENABLE

RW 0x0

Reserved

DMA_RESET

RW 0x0

FIFO_RESET

RW 0x0

CONTROLLER_RESET

RW 0x0

CTRL Fields

Bit Name Description Access Reset
25 USE_INTERNAL_DMAC 
Present only for the Internal DMAC configuration; else, it is reserved.
                                                0-The host performs data transfers through the slave interface
                                                1-Internal DMAC used for data transfer
Value Description
0x0 The host performs data transfers through the slave interface
0x1 Internal DMAC used for data transfer
RW 0x0
24 ENABLE_OD_PULLUP 
External open-drain pullup
                                                 0-Disable
                                                 1-Enable
                                                 Inverted value of this bit is output to ccmd_od_pullup_en_n port.
When bit is set, command output always driven in open-drive mode; that is, DWC_mobile_storage drives either 0 or high impedance, and does not drive hard 1.
Value Description
0x0 Disable
0x1 Enable
RW 0x0
23:20 CARD_VOLTAGE_B 
Card regulator-B voltage setting; output to card_volt_b port.
Optional feature; ports can be used as general-purpose outputs
 RW 0x0
19:16 CARD_VOLTAGE_A 
Card regulator-A voltage setting; output to card_volt_a port.
Optional feature; ports can be used as general-purpose outputs
 RW 0x0
11 CEATA_DEVICE_INTERRUPT_STATUS 
0-Interrupts not enabled in CE-ATA device
                                                 1-Interrupts are enabled in CE-ATA device
Value Description
0x0 Interrupts not enabled in CE-ATA device
0x1 Interrupts are enabled in CE-ATA device
RW 0x0
10 SEND_AUTO_STOP_CCSD 
0-Clear bit if DWC_mobile_storage does not reset the bit
                                                 1-Send internally generated STOP after sending CCSD to
CE-ATA device
Value Description
0x0 Clear bit if DWC_mobile_storage does not reset the bit
0x1 Send internally generated STOP after sending CCSD to CE-ATA device
RW 0x0
9 SEND_CCSD 
0-Clear this bit if DWC_mobile_storage does not reset the bit                                                      
1-Send Command Completion Signal Disable (CCSD) to CE-ATA
device
Value Description
0x0 Clear bit if DWC_mobile_storage does not reset the bit
0x1 Send Command Completion Signal Disable (CCSD) to CE-ATA device
RW 0x0
8 ABORT_READ_DATA 
0-No change
                                                 1-After suspend command is issued during read-transfer, software
polls card to find when suspend happened. Once suspend occurs,software sets bit to reset data state-machine, which is waiting for next block of data. Bit automatically clears once data statemachine resets to idle.
Used in SDIO card suspend sequence.
Value Description
0x0 No change
0x1 Reset data state-machine
RW 0x0
7 SEND_IRQ_RESPONSE 
0-No Change in this
                                                 1-Send auto IRQ response
                                                 Bit automatically clears once response is sent.
To wait for MMC card interrupts, host issues CMD40, and DWC_mobile_storage waits for interrupt response from MMC card(s). In meantime, if host wants DWC_mobile_storage to exit waiting for interrupt state, it can set this bit, at which time DWC_mobile_storage command state-machine sends CMD40 response on bus and returns to idle state.
Value Description
0x0 No change
0x1 Send auto IRQ response
RW 0x0
6 READ_WAIT 
0-Clear read wait
                                                 1-Assert read wait
                                                 For sending read-wait to SDIO cards.
Value Description
0x0 Clear read wait
0x1 Assert read wait
RW 0x0
5 DMA_ENABLE 
0-Disable DMA transfer mode
                                                 1-Enable DMA transfer mode
                                                 Valid only if DWC_mobile_storage configured for External DMA interface.
Value Description
0x0 Disable DMA transfer mode
0x1 Enable DMA transfer mode
RW 0x0
4 INT_ENABLE 
Global interrupt enable/disable bit:
                                                 0-Disable interrupts
                                                 1-Enable interrupts
                                                 The int port is 1 only when this bit is 1 and one or more unmasked
interrupts are set.
Value Description
0x0 Disable interrupts
0x1 Enable interrupts
RW 0x0
2 DMA_RESET 
0-No change
                                                 1-Reset internal DMA interface control logic
                                                 To reset DMA interface, firmware should set bit to 1. This bit is
auto-cleared after two AHB clocks.
Value Description
0x0 No change
0x1 Reset internal DMA interface control logic
RW 0x0
1 FIFO_RESET 
0-No change
                                                 1-Reset to data FIFO To reset FIFO pointers
                                                 To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation.
Value Description
0x0 No change
0x1 Reset to data FIFO To reset FIFO pointer
RW 0x0
0 CONTROLLER_RESET 
0-No change
                                                 1-Reset DWC_mobile_storage controller
                                                 To reset controller, firmware should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles.
                                                 This resets:
                                                 * BIU/CIU interface
                                                 * CIU and state machines
                                                 * abort_read_data, send_irq_response, and read_wait bits of Control register
                                                 * start_cmd bit of Command register
                                                 Does not affect any registers or DMA interface, or FIFO or host
interrupts
Value Description
0x0 No change
0x1 Reset DWC_mobile_storage controller
RW 0x0