IDINTEN

         
Name: Internal DMAC Interrupt Enable Register
Size: 32 bits
Address Offset: 0x90
Read/Write access: read/write

Module Instance	Base Address	Register Address
`i_sdmmc_sdmmc_block_1`	`0xFF8D1000`	`0xFF8D1090`

Size: 32

Offset: 0x90

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`AI` `RW 0x0`	`NI` `RW 0x0`	`Reserved`		`CES` `RW 0x0`	`DU` `RW 0x0`	`Reserved`	`FBE` `RW 0x0`	`RI` `RW 0x0`	`TI` `RW 0x0`

IDINTEN Fields

Bit

Name

Description

Access

Reset

AI

Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits:
                                                 ■ IDINTEN[2] - Fatal Bus Error Interrupt
                                                 ■ IDINTEN[4] -  DU Interrupt

Value	Description
0x0	An abnormal interrupt is disabled
0x1	An abnormal interrupt is enabled

RW

0x0

NI

Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits:
                                                 ■ IDINTEN[0] - Transmit Interrupt
                                                 ■ IDINTEN[1] - Receive Interrupt

Value	Description
0x0	A normal interrupt is disabled
0x1	A normal interrupt is enabled

RW

0x0

CES

Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary.

Value	Description
0x0	The Card Interrupt summary is disabled
0x1	The Card Interrupt summary is enabled

RW

0x0

DU

Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled.

Value	Description
0x0	The Descriptor Unavailable interrupt is disabled
0x1	When set along with Abnormal Interrupt Summary Enable, the Descriptor Unavailable interrupt is enabled

RW

0x0

FBE

Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled.

Value	Description
0x0	Fatal Bus Error Enable Interrupt is disabled
0x1	When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled

RW

0x0

RI

Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled.

Value	Description
0x0	Receive Interrupt is disabled
0x1	When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled

RW

0x0

TI

Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled.

Value	Description
0x0	Transmit Interrupt is disabled
0x1	When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled

RW

0x0