reg_sbcfg6
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010074

Size: 32

Offset: 0x74

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_t_param_dqstrk_to_valid

RW 0x0

cfg_t_param_dqstrk_to_valid_last

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_period_dqstrk_interval

RW 0x0

reg_sbcfg6 Fields

Bit Name Description Access Reset
31:24 cfg_t_param_dqstrk_to_valid 
iohmc_ctrl_mmr_top_inst.cfg_t_param_dqstrk_to_valid[7:0]
Name:DQS Tracking Rd to Valid timing for Ranks other than the Last
Description:DQS Tracking Rd to Valid timing for Ranks other than the Last.
RW 0x0
23:16 cfg_t_param_dqstrk_to_valid_last 
iohmc_ctrl_mmr_top_inst.cfg_t_param_dqstrk_to_valid_last[7:0]
Name:DQS Tracking Rd to Valid timing for the last Rank
Description:DQS Tracking Rd to Valid timing for the last Rank.
RW 0x0
15:0 cfg_period_dqstrk_interval 
iohmc_ctrl_mmr_top_inst.cfg_period_dqstrk_interval[15:0]
Name:Periodic DQS Tracking Interval
Description:Interval between two controller controlled periodic DQS tracking.
RW 0x0