DOEPDMA5 

         Device OUT Endpoint 5 DMA Address Register
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB00BB4
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB40BB4

Size: 32

Offset: 0xBB4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DMAAddr

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMAAddr

RW 0x0

DOEPDMA5 Fields

Bit Name Description Access Reset
31:0 DMAAddr 
 Holds the start address of the external memory for storing or fetching endpoint
data.
Note: For control endpoints, this field stores control OUT data packets as well as
SETUP transaction data packets. When more than three SETUP packets are
received back-to-back, the SETUP data packet in the memory is overwritten.
This register is incremented on every AHB transaction. The application can give
only a DWORD-aligned address.
 When Scatter/Gather DMA mode is not enabled, the application programs the
start address value in this field.
 When Scatter/Gather DMA mode is enabled, this field indicates the base
pointer for the descriptor list.
 RW 0x0