mpfe_config
MPFE Interface Select
Module Instance | Base Address | Register Address |
---|---|---|
i_sys_mgr_core | 0xFFD12000 | 0xFFD12228 |
Size: 32
Offset: 0x228
Access: RW
Access mode: PRIVILEGEMODE | SECURE
Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
mpfeintfcsel_spare_out RW 0x0 |
mpfeintfcsel_C RW 0x0 |
mpfeintfcsel_AB RW 0x0 |
mpfe_config Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
15:2 | mpfeintfcsel_spare_out |
The spare MPFE - HPS spare ports and registers are implemented as a contingency in the event MPFE-Fabric-IO96-HMC issues arise that need management by HPS or SDM firmware. |
RW | 0x0 |
1 | mpfeintfcsel_C |
To select if Fabric bypass path or MPFE path of signals conect to Tile C 0 = select the Fabric bypass path for the IO48 in the IO96 identified as TILE C 1 = select the MPFE path for the IO48 in the IO96 identified as TILE C |
RW | 0x0 |
0 | mpfeintfcsel_AB |
To select if Fabric bypass path or MPFE path of signals conect to Tile A/B 0 = select the Fabric bypass path for the IO48 in the IO96 identified as TILE A and Tile B 1 = select the MPFE path for the IO48 in the IO96 identified as TILE A and Tile B |
RW | 0x0 |