cs_setup_cnt

         Chip select setup/tWB time

Module Instance	Base Address	Register Address
`i_nand_config`	`0xFFB80000`	`0xFFB80220`

Size: 32

Offset: 0x220

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`														`twb` `RW 0xA`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`twb` `RW 0xA`				`Reserved`							`value` `RW 0x3`

cs_setup_cnt Fields

Bit	Name	Description	Access	Reset
17:12	`twb`	Number of clk_x cycles required for meeting the tWB time. This register refers to device timing parameter TWB.	`RW`	`0xA`
4:0	`value`	Number of clk_x cycles required for meeting chip select setup time. This register refers to device timing parameter Tcs. The value in this registers reflects the extra setup cycles for chip select before read/write enable signal is set low. The default value is calculated for ONFI Timing mode 0 Tcs = 70ns and maximum clk_x period of 4ns for 1x/5x clock multiple for 20ns cycle time device. Please refer to Figure 3.3 for the relationship between the cs_setup_cnt and rdwr_en_lo_cnt values.	`RW`	`0x3`

Bit

Name

Description

Access

Reset

17:12

twb

Number of clk_x cycles required for meeting the tWB time. This register
                               refers to device timing parameter TWB.

RW

0xA

4:0

value

Number of clk_x cycles required for meeting chip select setup time. This register
                               refers to device timing parameter Tcs. The value in this registers reflects the extra
                               setup cycles for chip select before read/write enable signal is set low. The default value 
                               is calculated for ONFI Timing mode 0 Tcs = 70ns and maximum clk_x period of 4ns for 
                               1x/5x clock multiple for 20ns cycle time device.
                               Please refer to Figure 3.3 for the relationship between the cs_setup_cnt and rdwr_en_lo_cnt values.

RW

0x3