pllglob

if lostlock_bypass_en is set and the PLL looses lock, channel bypass signal is asserted by HW. 
To provide glitchless clock to downstream logic even if lock toggles , this sticky bit is provided. 
SW is supposed to monitor the lock signal for some time and if the signal is stable then SW can write '1' into this register to clear lostlock_bypass mode

1: Clear PLL's lostlock bypass mode
0: no effect on PLL lostlock bypass mode

When bypass enable of all the 4 channels go low HW clears this register.

When PLL looses lock, the PLL output clocks are muted. 
Clock manager will not have any clock to recover or even process lostlock interrupt. 
This bit when set will enable the periph PLL to give keepalive clock at the output upon loosing lock

1: Turns on bypass to keepalive clock feature upon PLL's loss of lock
0:Turns OFF bypass to keepalive clock feature upon PLL's loss of lock

Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will
gate the clock coming out from the divider.
This control can be only changed while the HP PLL IP is at Reset or PD. The reference clock divider value has
to be set to ensure that the following condition is always met:
3*( Fref/ictl_pll_ arefdiv_nt_[3:0]) ≤Fvco /ictl_pll_moddiv_nt_[3:0] if ictl_pll_fastref_en_nt = 0.
1.5*( Fref/ictl_pll_ arefdiv_nt_[3:0]) ≤Fvco /ictl_pll_moddiv_nt_[3:0] if ictl_pll_fastref_en_nt = 1

HP PLL fast reference clock mode control.
0 - Input reference clock is <=200MHz
1 - Input reference clock is > 200MHz

Disconnect clock disable control. It is used to glitchlessly disable all keepalive clock in disconnect state.
0—Enable
1—Disable

Clock slice output synchronization request control. Once asserted, the positive edge of all enabled clock slices will be aligned.
1- Request clock synchronization. The output clock slice status of all enabled clock slices will drop to 0.
0 – Once all clock slice status have dropped to 0, ictl_pll_clksync_a must be set to 0. No clock will be output until the ictl_pll_clksync_a has been de-asserted.

HP PLL Internal Power-gated State Control
0—Normal State
1—Internally Power-gated state.

Controls the VCO input clock source.

Reference clock divider control used by the DPLL. The effective divider value is 2^(ictl_pll_drefdiv_nt_[1:0]).
This control can be only changed while the HP PLL IP is at Reset or PD. The DPLL reference clock divider has to be set to ensure that the following condition is always met:
Fref/(2^ictl_pll_drefdiv_nt_[1:0]) ≤ 200 MHz

Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will gate the clock coming out from the divider.
This control can be only changed while the HP PLL IP is at Reset or PD. The reference clock divider value has to be set to ensure that the following condition is always met:
3*( Fref/ictl_pll_ arefdiv_nt_[3:0]) ≤Fvco /ictl_pll_moddiv_nt_[3:0] if ictl_pll_fastref_en_nt = 0.
1.5*( Fref/ictl_pll_ arefdiv_nt_[3:0]) ≤Fvco /ictl_pll_moddiv_nt_[3:0] if ictl_pll_fastref_en_nt = 1.

Power-On Reset. Used to initialize memory and reset the Power Management Unit (PMU). The minimum POR assertion time required is 0.5 µs.
1—Exit POR (Hard Reset Is De-Asserted)
0—In POR (Hard Reset Is Asserted)
(By default the signal is asserted. Software should come and write '1' in this reg to bring up the PLL.)

Keepalive clock power down control
0—Power Down
1—Power up
Keepalive clock can only be powered down in disconnect or disconnect quiet state and ictl_pll_keepalive_disable_a must be set to 1’b1 before asserting power down keepalive clock.
(By default the signal is asserted.