IC_CON

Reserved bits - Read Only

Reserved bits - Read Only

Reserved bits - Read Only

Reserved bits - Read Only

Reserved bits - Read Only

Reserved bits - Read Only

Reserved bits - Read Only

In Master mode:
1'b1: issues the STOP_DET interrupt only when master is active.
1'b0: issues the STOP_DET irrespective of whether master is active or not.
Dependencies: This Register bit value is applicable only when IC_STOP_DET_IF_MASTER_ACTIVE=1 and IC_ULTRA_FAST_MODE=0
Reset value: 0x0.

This bit controls whether 
DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH,
as described in the IC_RX_FULL_HLD_BUS_EN parameter. 
Dependencies: This register bit value is applicable only when the
IC_RX_FULL_HLD_BUS_EN configuration parameter is set to 1 and IC_ULTRA_FAST_MODE=0
If IC_RX_FULL_HLD_BUS_EN = 0, then this bit is read-only. 
If IC_RX_FULL_HLD_BUS_EN = 1, then this bit can be read or write.
Reset value: 0x0.

This bit controls the generation 
of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
Reset value: 0x0.

In slave mode:
1:  issues the STOP_DET interrrupt only when it is addressed.
0:  issues the STOP_DET irrespective of whether it's addressed or not.
Dependencies: This register bit value is applicable in the slave mode only (MASTER_MODE = 1'b0)
Reset value: 0x0
NOTE: During a general call address, this slave does not issue the 
STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if
the slave responds to the general call address by generating ACK.
The STOP_DET interrupt is generated only when the transmitted
address matches the slave address (SAR).

This bit controls whether I2C has its slave disabled,
which means once the presetn signal is applied, then
this bit takes on the value of the configuration parameter
IC_SLAVE_DISABLE. You have the choice of having the slave enabled
or disabled after reset is applied, which means software does not
have to configure the slave. By default, the slave is always enabled
(in reset state as well). If you need to disable it after reset, set
this bit to 1.
If this bit is set (slave is disabled), DW_apb_i2c functions only as
a master and does not perform any action that requires a slave.
0: slave is enabled
1: slave is disabled
Reset value: IC_SLAVE_DISABLE configuration parameter
NOTE: Software should ensure that if this bit is written with 0,
then bit 0 should also be written with a 0.

Determines whether RESTART conditions may be sent when
acting as a master. Some older slaves do not support handling
RESTART conditions; however, RESTART conditions are used in
several DW_apb_i2c operations.
0: disable
1: enable
When RESTART is disabled, the master is prohibited from
performing the following functions:
- Change direction within a transfer (split)
- Send a START BYTE
- High-speed mode operation
- Combined format transfers in 7-bit addressing modes
- Read operation with a 10-bit address
- Send multiple bytes per transfer
By replacing RESTART condition followed by a STOP and a
subsequent START condition, split operations are broken down
into multiple DW_apb_i2c transfers. If the above operations are
performed, it will result in setting bit 6 (TX_ABRT) of the
IC_RAW_INTR_STAT register.
Reset value: IC_RESTART_EN configuration parameter

If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is
set to 'No' (0), this bit is named IC_10BITADDR_MASTER and
controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit
addressing mode when acting as a master.
If I2C_DYNAMIC_TAR_UPDATE is set to 'Yes' (1), the
function of this bit is handled by bit 12 of IC_TAR register, and
becomes a read-only copy called
IC_10BITADDR_MASTER_rd_only.
0: 7-bit addressing
1: 10-bit addressing
Dependencies: If I2C_DYNAMIC_TAR_UPDATE = 1, then this
bit is read-only. If I2C_DYNAMIC_TAR_UPDATE = 0, then this
bit can be read or write.
Reset value: IC_10BITADDR_MASTER configuration
parameter

When acting as a slave, this bit controls whether the DW_apb_i2c
responds to 7- or 10-bit addresses.
0: 7-bit addressing. The DW_apb_i2c ignores transactions that
   involve 10-bit addressing; for 7-bit addressing,
   only the lower 7 bits of the IC_SAR register are compared.
1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit
   addressing transfers that match the full 10 bits of the IC_SAR
   register.
Reset value: IC_10BITADDR_SLAVE configuration parameter

These bits control at which speed the DW_apb_i2c operates; its
setting is relevant only if one is operating the DW_apb_i2c in
master mode. Hardware protects against illegal values being
programmed by software. This register should be programmed
only with a value in the range of 1 to IC_MAX_SPEED_MODE;
otherwise, hardware updates this register with the value of
IC_MAX_SPEED_MODE.
1: standard mode (100 kbit/s)
2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
3: high speed mode (3.4 Mbit/s)
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: IC_MAX_SPEED_MODE configuration

This bit controls whether the DW_apb_i2c master is enabled.
0: master disabled
1: master enabled
Reset value: IC_MASTER_MODE configuration parameter
NOTE: Software should ensure that if this bit is written with '1'
then bit 6 should also be written with a '1'.