emac0 

         Registers used by the EMAC. All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD12044

Size: 32

Offset: 0x44

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

axi_disable

RW 0x0

sbd_data_endianness

RW 0x0

awprot

RW 0x2

arprot

RW 0x2

awcache

RW 0x0

arcache

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ptp_ref_sel

RW 0x0

Reserved

phy_intf_sel

RW 0x3

emac0 Fields

Bit Name Description Access Reset
31 axi_disable 
AXI Disable
 RW 0x0
30 sbd_data_endianness 
Specifies the endianness of the EMAC DMA transfers.
The field array index corresponds to the EMAC index.
Value Description
0 little_endian
1 big_endian
RW 0x0
29:27 awprot 
Specifies the values of the 2 EMAC AWCACHE signals.
==========================
AxPROT[1]
  LOW:  Secure Access
  HIGH: NonSecure Access
==========================
AxPROT[0]
  LOW:  Normal Access
  HIGH: Privileged Access
==========================
Value Description
0 Secure Normal(non-privileged) access
1 Secure Privileged access
2 Non-Secure Normal(non-privileged) access
3 Non-Secure Privileged access
RW 0x2
26:24 arprot 
Specifies the values of the ARPROT signals.
==========================
AxPROT[1]
  LOW:  Secure Access
  HIGH: NonSecure Access
==========================
AxPROT[0]
  LOW:  Normal Access
  HIGH: Privileged Access
==========================
Value Description
0 Secure Normal(non-privileged) access
1 Secure Privileged access
2 Non-Secure Normal(non-privileged) access
3 Non-Secure Privileged access
RW 0x2
23:20 awcache 
Specifies the values of the 2 EMAC AWCACHE signals.
The field array index corresponds to the EMAC index.
Value Description
0 Noncache_Nonbuff
1 Buff
2 Cache_Nonalloc
3 Cache_Buff_Nonalloc
4 Reserved1
5 Reserved2
6 Cache_Wrthru_Rdalloc
7 Cache_Wrback_Rdalloc
8 Reserved3
9 Reserved4
10 Cache_Wrthru_Wralloc
11 Cache_Wrback_Wralloc
12 Reserved5
13 Reserved6
14 Cache_Wrthru_Alloc
15 Cache_Wrback_Alloc
RW 0x0
19:16 arcache 
Specifies the values of the 2 EMAC ARCACHE signals.
The field array index corresponds to the EMAC index.
Value Description
0 Noncache_Nonbuff
1 Buff
2 Cache_Nonalloc
3 Cache_Buff_Nonalloc
4 Reserved1
5 Reserved2
6 Cache_Wrthru_Rdalloc
7 Cache_Wrback_Rdalloc
8 Reserved3
9 Reserved4
10 Cache_Wrthru_Wralloc
11 Cache_Wrback_Wralloc
12 Reserved5
13 Reserved6
14 Cache_Wrthru_Alloc
15 Cache_Wrback_Alloc
RW 0x0
8 ptp_ref_sel 
This field selects if the Timestamp reference is internally or externally generated.  EMAC0 may be the master to generate the timestamp for EMAC1 and EMAC2.   EMAC0 must be set to Internal Timestamp.   EMAC1/2 may be set to either Internal or External.
Value Description
0 internal
1 external
RW 0x0
1:0 phy_intf_sel 
PHY Interface Select
Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY interface.  Note, the MAC speed is an output of Synopsys IP.    So the System Manager PHY Select combined with MAC speed from the IP determine the clock/PHY configuration.  "Out of Reset" mode implies that the MAC RX and TX internal clocks use the Clock Manager reference rather than depending on the PHY to have active clocks.
Value Description
0 GMII_MII
1 RGMII
2 RMII
3 RESET
RW 0x3