PMCNTENCLR

         Performance Monitor Counter Enable Clear registers are used to disable the event counters PMEVCNTRxx.

Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA003C20`

Size: 32

Offset: 0x3C20

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`												`P19` `WO 0x0`	`P18` `WO 0x0`	`P17` `WO 0x0`	`P16` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`P15` `WO 0x0`	`P14` `WO 0x0`	`P13` `WO 0x0`	`P12` `WO 0x0`	`P11` `WO 0x0`	`P10` `WO 0x0`	`P9` `WO 0x0`	`P8` `WO 0x0`	`P7` `WO 0x0`	`P6` `WO 0x0`	`P5` `WO 0x0`	`P4` `WO 0x0`	`P3` `WO 0x0`	`P2` `WO 0x0`	`P1` `WO 0x0`	`P0` `WO 0x0`