GHWCFG1

         User HW Config1 Register

Module Instance	Base Address	Register Address
`i_usbotg_0_DWC_otg_intreg`	`0xFFB00000`	`0xFFB00044`
`i_usbotg_1_DWC_otg_intreg`	`0xFFB40000`	`0xFFB40044`

Size: 32

Offset: 0x44

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`EpDir` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`EpDir` `RO 0x0`

GHWCFG1 Fields

Bit	Name	Description	Access	Reset
31:0	`EpDir`	This 32-bit field uses two bits per endpoint to determine the endpoint direction. Endpoint Bits [31:30]: Endpoint 15 direction Bits [29:28]: Endpoint 14 direction ... Bits [3:2]: Endpoint 1 direction Bits[1:0]: Endpoint 0 direction (always BIDIR) Direction 2'b00: BIDIR (IN and OUT) endpoint 2'b01: IN endpoint 2'b10: OUT endpoint 2'b11: Reserved	`RO`	`0x0`

Bit

Name

Description

Access

Reset

31:0

EpDir

This 32-bit field uses two bits per 
endpoint to determine the endpoint direction.
Endpoint
 Bits [31:30]: Endpoint 15 direction
 Bits [29:28]: Endpoint 14 direction
...
 Bits [3:2]: Endpoint 1 direction
 Bits[1:0]: Endpoint 0 direction (always BIDIR)
Direction
 2'b00: BIDIR (IN and OUT) endpoint
 2'b01: IN endpoint
 2'b10: OUT endpoint
 2'b11: Reserved

RO

0x0