max_rd_delay

         Max round trip read data delay for data capture

Module Instance	Base Address	Register Address
`i_nand_config`	`0xFFB80000`	`0xFFB80210`

Size: 32

Offset: 0x210

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`												`value` `RW 0x0`

max_rd_delay Fields

Bit	Name	Description	Access	Reset
3:0	`value`	Number of clk_x cycles after generation of feedback clk_x_out pulse when it is safe to synchronize received data to clk_x domain. Data should have been registered with clk_x_in and stable by the time max_rd_delay cycles has elapsed. Please see timing diagram in bus interface timing section of this guide for further elaboration. A default value of zero will mean a value of clk_x multiple minus one.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

3:0

value

Number of clk_x cycles after generation of feedback clk_x_out pulse when it is safe
                               to synchronize received data to clk_x domain. Data should have been registered with
                               clk_x_in and stable by the time max_rd_delay cycles has elapsed. Please see timing
                               diagram in bus interface timing section of this guide for further elaboration. A 
                               default value of zero will mean a value of clk_x multiple minus one.

RW

0x0