IC_RAW_INTR_STAT

Reserved bits - Read Only

Reserved bits - Read Only

Indicates whether master is holding the bus and TX FIFO is empty.
Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.
Reset value: 0x0

Indicates whether a RESTART condition has occurred on the I2C interface 
when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.
(Note:Following are exceptions where the Restart interrupt will not get generated.
In the case of High speed Mode or Startbyte transfer, where the Restart comes before the Address field as per the 
I2C protocol defined format, the Slave is still not in the addressed mode and hence will not generate the RESTART_DET interrupt.)
Reset value: 0x0

Set only when a General Call address is received and it is acknowledged. It
stays set until it is cleared either by disabling DW_apb_i2c or when the CPU
reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the
received data in the Rx buffer.
Reset value: 0x0

Indicates whether a START or RESTART condition has occurred on the I2C
interface regardless of whether DW_apb_i2c is operating in slave or master
mode.
Reset value: 0x0

Indicates whether a STOP condition 
has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
In Slave Mode:
If IC_CON[7]=1'b1  (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed.
Note: During general call address, this slave will not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, 
even if slave responds for general call address by generating ACK.
The STOP_DET interrupt is generated only when the transmitted address matches with the slave address(SAR).

If IC_CON[7]=1'b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether it's being addressed.

In Master Mode:
if IC_CON[10]=1'b1  (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active.

If IC_CON[10]=1'b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not.

In Master mode, this field is not dependent on  IC_CON[10] (STOP_DET_IF_MASTER_ACTIVE) when IC_ULTRA_FAST_MODE=1
Reset value: 0x0

This bit captures DW_apb_i2c activity and stays set until it is cleared. There
are four ways to clear it:
- Disabling the DW_apb_i2c
- Reading the IC_CLR_ACTIVITY register
- Reading the IC_CLR_INTR register
- System reset
Once this bit is set, it stays set unless one of the four methods is used to clear it.
Even if the DW_apb_i2c module is idle, this bit remains set until cleared,
indicating that there was activity on the bus.
Reset value: 0x0

When the DW_apb_i2c is acting as a slave-transmitter,
this bit is set to 1 if the master does not acknowledge
a transmitted byte. This occurs on the last byte of
the transmission, indicating that the transmission is done.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0

This bit indicates if DW_apb_i2c, as an I2C transmitter,
is unable to complete the intended actions on the
contents of the transmit FIFO. This situation can
occur both as an I2C master or an I2C slave, and is
referred to as a 'transmit abort'.
When this bit is set to 1, the IC_TX_ABRT_SOURCE register
indicates the reason why the transmit abort takes places.
NOTE: The DW_apb_i2c flushes/resets/empties only the TX_FIFO whenever
there is a transmit abort caused by any of the events tracked by the
IC_TX_ABRT_SOURCE register. The Tx FIFO remains in this flushed state
until the register IC_CLR_TX_ABRT is read. Once this read is performed, the
Tx FIFO is then ready to accept more data bytes from the APB interface. RX
FIFO flush because of TX_ABRT is controlled by the coreConsultant parameter IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT.
Reset value: 0x0

This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C
master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds
the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means
that the slave has been addressed by a remote master that is asking for data to
be transferred. The processor must respond to this interrupt and then write the
requested data to the IC_DATA_CMD register. This bit is set to 0 just after the
processor reads the IC_CLR_RD_REQ register.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0

The behavior of the TX_EMPTY interrupt status 
differs based on the TX_EMPTY_CTRL selection in the IC_CON register.
 When TX_EMPTY_CTRL = 0:
   This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
 When TX_EMPTY_CTRL = 1:
   This bit is set to 1 when the transmit buffer is at or below the threshold value.

set in the IC_TX_TL register and the transmission of the address/data from 
the internal shift register for the most recently popped command is completed.
It is automatically cleared by hardware when the buffer level goes above the
threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in
reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1,
provided there is activity in the master or slave state machines. When there is no
longer any activity, then with ic_en=0, this bit is set to 0.
Reset value: 0x0.

Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH
and the processor attempts to issue another I2C command by writing to the
IC_DATA_CMD register. When the module is disabled, this bit keeps its level
until the master or slave state machines go into idle, and when ic_en goes to 0,
this interrupt is cleared.
Reset value: 0x0

Set when the receive buffer reaches or goes above the RX_TL threshold in the
IC_RX_TL register. It is automatically cleared by hardware when buffer level
goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the
RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this
bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of
the activity that continues.
Reset value: 0x0

Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
an additional byte is received from an external I2C device. The DW_apb_i2c
acknowledges this, but any data bytes received after the FIFO is full are lost. If
the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the
master or slave state machines go into idle, and when ic_en goes to 0, this
interrupt is cleared.
NOTE: If the parameter IC_RX_FULL_HLD_BUS_EN=1, then the RX_OVER interrupt is
never set to 1, because the criteria to set this interrupt are never met.
Reset value: 0x0

Set if the processor attempts to read the receive buffer when it is empty by
reading from the IC_DATA_CMD register. If the module is disabled
(IC_ENABLE[0]=0), this bit keeps its level until the master or slave state
machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
Reset value: 0x0