reg_sideband1

         Sideband 1 Register

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF80100B0`

Size: 32

Offset: 0xB0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`												`mmr_refresh_req` `RW 0x0`

reg_sideband1 Fields

Bit	Name	Description	Access	Reset
3:0	`mmr_refresh_req`	iohmc_ctrl_mmr_top_inst.mmr_refresh_req[3:0] Name:User Refresh Request Description:When asserted, indicates Refresh request to the specific rank. Each bit corresponds to each rank. Controller clear this bit to ‘0’ once Refresh is executed. Note: User may program any combination of values.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

3:0

mmr_refresh_req

iohmc_ctrl_mmr_top_inst.mmr_refresh_req[3:0]
Name:User Refresh Request
Description:When asserted, indicates Refresh request to the specific rank. Each bit corresponds to each rank. Controller clear this bit to ‘0’ once Refresh is executed.
Note: User may program any combination of values.

RW

0x0