reg_3ds1

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF8010128`

Size: 32

Offset: 0x128

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`									`cfg_3ds_ref2ref_dlr` `RW 0x0`

reg_3ds1 Fields

Bit	Name	Description	Access	Reset
6:0	`cfg_3ds_ref2ref_dlr`	iohmc_ctrl_mmr_top_inst.cfg_3ds_ref2ref_dlr[6:0] Name:Refresh-to-refresh timing (Between Different Logical Ranks) Description:Timing parameter for refreshes between different logical ranks i.e. tRFC (DLR).	`RW`	`0x0`

Bit

Name

Description

Access

Reset

6:0

cfg_3ds_ref2ref_dlr

iohmc_ctrl_mmr_top_inst.cfg_3ds_ref2ref_dlr[6:0]
Name:Refresh-to-refresh timing (Between Different Logical Ranks)
Description:Timing parameter for refreshes between different logical ranks i.e. tRFC (DLR).

RW

0x0