IC_FS_SPKLEN

         Name: I2C SS, FS or FM+  spike suppression limit
Size: 8 bits
Address: 0xA0
Read/Write Access: Read/Write
This register is used to store the duration, measured in ic_clk cycles,
of the longest spike that is filtered out by the spike suppression logic w
hen the component is operating in SS, FS or FM+ modes. 
The relevant I2C requirement is tSP (table 4) as detailed in the 
I2C Bus Specification. This register must be programmed with a minimum value of 1.
Dependencies: This register is not applicable  when IC_ULTRA_FAST_MODE=1

Module Instance	Base Address	Register Address
`sdm_i_i2c_0_DW_apb_i2c_addr_block1`	`0xFF8D0100`	`0xFF8D01A0`
`sdm_i_i2c_1_DW_apb_i2c_addr_block1`	`0xFF8D0200`	`0xFF8D02A0`

Size: 32

Offset: 0xA0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_IC_FS_SPKLEN` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_IC_FS_SPKLEN` `RO 0x0`								`IC_FS_SPKLEN` `RW 0x2`

IC_FS_SPKLEN Fields

Bit	Name	Description	Access	Reset
31:8	`RSVD_IC_FS_SPKLEN`	Reserved bits - Read Only	`RO`	`0x0`
7:0	`IC_FS_SPKLEN`	This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. Default Reset value: IC_DEFAULT_FS_SPKLEN configuration parameter.	`RW`	`0x2`

Bit

Name

Description

Access

Reset

31:8

RSVD_IC_FS_SPKLEN

Reserved bits - Read Only

RO

0x0

7:0

IC_FS_SPKLEN

This register must be set before any I2C bus transaction can take place to
ensure stable operation. This register sets the duration, measured in ic_clk cycles,
of the longest spike in the SCL or SDA lines that will be filtered out by the spike 
suppression logic.
This register can be written only when the I2C interface is disabled which
corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times
have no effect.
The minimum valid value is 1; hardware prevents values less than this being
written, and if attempted results in 1 being set. 
Default Reset value: IC_DEFAULT_FS_SPKLEN configuration parameter.

RW

0x2