GIC_VCPUifHypAlias2 Address Map

Memory map allowing access to the GIC virtual CPU interface control registers for CPU2 from any processor. Contains all registers with the GICH prefix. Note: This provides a means for other processors to access the virtual CPU interface control registers for CPU2. It is expected that this block will only be made accessible to hypervisors. For details of these registers, please refer to the Arm https://developer.arm.com/docs/ddi0471/b Corelink GIC-400 Generic Interrupt Controller Technical Reference Manual.
Module Instance Base Address End Address
i_gic_wrapper_VCPUifHypAlias2 0xFFFC5400 0xFFFC55FF
Register Offset Width Access Reset Value Description
GICH_HCR 0x0 32 RW 0x00000000 
Hypervisor Control Register
GICH_VTR 0x4 32 RO 0x90000003 
VGIC Type Register
GICH_VMCR 0x8 32 RW 0x004C0000 
Virtual Machine Control Register
GICH_MISR 0x10 32 RO 0x00000000 
Maintenance Interrupt Status Register
GICH_EISR0 0x20 32 RO 0x00000000 
End of Interrupt Status Register
GICH_ELSR0 0x30 32 RO 0x0000000F 
Empty List register Status Register
GICH_APR0 0xF0 32 RW 0x00000000 
Active Priority Register
GICH_LR0 0x100 32 RW 0x00000000 
List Register 0
GICH_LR1 0x104 32 RW 0x00000000 
List Register 1
GICH_LR2 0x108 32 RW 0x00000000 
List Register 2
GICH_LR3 0x10C 32 RW 0x00000000 
List Register 3