GNPTXFSIZ 

         Non-periodic Transmit FIFO Size Register
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB00028
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB40028

Size: 32

Offset: 0x28

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NPTXFDep

RW 0x2000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NPTXFStAddr

RW 0x2000

GNPTXFSIZ Fields

Bit Name Description Access Reset
31:16 NPTXFDep 
Mode: Host only
Non-periodic TxFIFO Depth (NPTxFDep)
For host mode, this field is always valid.
For Device mode, this field is valid for shared fifo 
This value is in terms of 32-bit words.
 Minimum value is 16
 Maximum value is 32,768
Programmed values must not exceed the power-on value.
Mode: Device only
IN Endpoint TxFIFO 0 Depth (INEPTxF0Dep)
This value is in terms of 32-bit words.
 Minimum value is 16
 Maximum value is 32,768
This field is determined by Enable Dynamic FIFO Sizing
Programmed values must not
exceed the power-on value.
RW 0x2000
15:0 NPTXFStAddr 
Mode: Host only
Non-periodic Transmit RAM Start Address (NPTxFStAddr)
For host mode, this field is always valid. This field contains the memory start address 
For Non-periodic Transmit FIFO RAM. 
Programmed values must not exceed the power-on value.
Mode: Device only
IN Endpoint FIFO0 Transmit RAM Start Address
(INEPTxF0StAddr)
This field contains the memory start address For IN Endpoint
Transmit FIFO# 0.
Programmed values must not exceed the power-on value.
 RW 0x2000