reg_3ds0
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010124

Size: 32

Offset: 0x124

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_3ds_pr_stag_enable

RW 0x0

cfg_cid_addr_width

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_3ds_lr_num3

RW 0x0

cfg_3ds_lr_num2

RW 0x0

cfg_3ds_lr_num1

RW 0x0

cfg_3ds_lr_num0

RW 0x0

reg_3ds0 Fields

Bit Name Description Access Reset
18 cfg_3ds_pr_stag_enable 
iohmc_ctrl_mmr_top_inst.cfg_3ds_pr_stag_enable
Name:Enable Physical Rank Staggering to 3DS devices
Description:1’b0 – Disable 3DS Physical Rank Refresh Staggering (Default)
1’b1 – Enable 3DS Physical Rank Refresh Staggering.
Note: This is the global enable bit. There is no per rank option.
RW 0x0
17:16 cfg_cid_addr_width 
iohmc_ctrl_mmr_top_inst.cfg_cid_addr_width[1:0]
Name:3DS Chip ID Address Width
Description:To configure the width of the 3DS Chip ID signal, range 0-3.
RW 0x0
15:12 cfg_3ds_lr_num3 
iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num3[3:0]
Name:Number of 3DS Logical Ranks on Physical Rank 3
Description:4’b0000: Disable 3DS Logic
4’b0001: 1H (engineering feature i.e. 3DS logic running in non-3DS mode)
4’b0010: 2H
4’b0100: 4H
4’b1000: 8H (engineering feature)
All other values are reserved.
RW 0x0
11:8 cfg_3ds_lr_num2 
iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num2[3:0]
Name:Number of 3DS Logical Ranks on Physical Rank 2
Description:4’b0000: Disable 3DS Logic
4’b0001: 1H (engineering feature i.e. 3DS logic running in non-3DS mode)
4’b0010: 2H
4’b0100: 4H
4’b1000: 8H (engineering feature)
All other values are reserved.
RW 0x0
7:4 cfg_3ds_lr_num1 
iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num1[3:0]
Name:Number of 3DS Logical Ranks on Physical Rank 1
Description:4’b0000: Disable 3DS Logic
4’b0001: 1H (engineering feature i.e. 3DS logic running in non-3DS mode)
4’b0010: 2H
4’b0100: 4H
4’b1000: 8H (engineering feature)
All other values are reserved.
RW 0x0
3:0 cfg_3ds_lr_num0 
iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num0[3:0]
Name:Number of 3DS Logical Ranks on Physical Rank 0
Description:4’b0000: Disable 3DS Logic
4’b0001: 1H (engineering feature i.e. 3DS logic running in non-3DS mode)
4’b0010: 2H
4’b0100: 4H
4’b1000: 8H (engineering feature)
All other values are reserved.
RW 0x0