reg_ctrlcfg6

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF8010040`

Size: 32

Offset: 0x40

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`cfg_cs_chip` `RW 0x0`

reg_ctrlcfg6 Fields

Bit	Name	Description	Access	Reset
15:0	`cfg_cs_chip`	iohmc_ctrl_mmr_top_inst.cfg_cs_chip[15:0] Name:CS to Chip Mapping Description:Chip select mapping scheme. Mapping separated into 4 sections: [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which CS_n signal should be active when command goes to current CS. Eg: if we set to 16’b0000_0000_0010_0001, CS_n signal will be active on CS0 and CS1 when command occurs on CS0 and CS1 respectively. Default value should be 16’b1000_0100_0010_0001, only change it for RDIMM single rank design where each RDIMM have 2 CS_n signal but only one is used for actual memory access, one more CS_n bit for RDIMM control word access.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

15:0

cfg_cs_chip

iohmc_ctrl_mmr_top_inst.cfg_cs_chip[15:0]
Name:CS to Chip Mapping
Description:Chip select mapping scheme.
Mapping separated into 4 sections: [CS3][CS2][CS1][CS0]
Each section consists of 4 bits to indicate which CS_n signal should be active when command goes to current CS.
Eg: if we set to 16’b0000_0000_0010_0001, CS_n signal will be active on CS0 and CS1 when command occurs on CS0 and CS1 respectively.
Default value should be 16’b1000_0100_0010_0001, only change it for RDIMM single rank design where each RDIMM have 2 CS_n signal but only one is used for actual memory access, one more CS_n bit for RDIMM control word access.

RW

0x0