coh_cpu0_bypass_I_main_QosGenerator_Priority

         Priority register.

Module Instance	Base Address	Register Address
`CCU_coh_cpu0_bypass_coh_cpu0_bypass_I_main_QosGenerator`	`0xF7100100`	`0xF7100108`

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`MARK` `RO 0x1`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`					`P1` `RW 0x7`			`Reserved`					`P0` `RW 0x3`

coh_cpu0_bypass_I_main_QosGenerator_Priority Fields

Bit	Name	Description	Access	Reset
31	`MARK`	Backward compatibility marker when 0.	`RO`	`0x1`
10:8	`P1`	In Regulator mode, defines the HIGH hurry level. In Fixed/Limiter mode, defines the Urgency level for READ transactions.	`RW`	`0x7`
2:0	`P0`	In Regulator mode, defines the LOW hurry level. In Fixed/Limiter mode, defines the Urgency level for WRITE transactions.	`RW`	`0x3`

Bit

Name

Description

Access

Reset

MARK

Backward compatibility marker when 0.

RO

0x1

10:8

P1

In Regulator mode, defines the HIGH hurry level. In Fixed/Limiter mode, defines the Urgency level for READ transactions.

RW

0x7

2:0

P0

In Regulator mode, defines the LOW hurry level. In Fixed/Limiter mode, defines the Urgency level for WRITE transactions.

RW

0x3