DSTS

         Device Status Register

Module Instance	Base Address	Register Address
`i_usbotg_0_DWC_otg_intreg`	`0xFFB00000`	`0xFFB00808`
`i_usbotg_1_DWC_otg_intreg`	`0xFFB40000`	`0xFFB40808`

Size: 32

Offset: 0x808

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED` `RO 0x0`								`DevLnSts` `RO 0x0`		`SOFFN` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`SOFFN` `RO 0x0`								`RESERVED1` `RO 0x0`				`ErrticErr` `RO 0x0`	`EnumSpd` `RO 0x1`		`SuspSts` `RO 0x0`

DSTS Fields

Bit

Name

Description

Access

Reset

31:24

RESERVED

RESERVED

RO

0x0

23:22

DevLnSts

Device Line Status (DevLnSts) 
Indicates the current logic level USB data lines 
  DevLnSts[1]: Logic level of D+ 
  DevLnSts[0]: Logic level of D-

RO

0x0

21:8

SOFFN

Frame or Microframe Number of the Received SOF (SOFFN)
When the core is operating at high speed, this field contains a
microframe number. When the core is operating at full or low
speed, this field contains a Frame number.
Note: This register may return a non zero value if read immediately after power on reset.
In case the register bit reads non zero immediately after power on reset it does not
indicate that SOF has been received from the host. The read value of this interrupt is
valid only after a valid connection between host and device is established.

RO

0x0

7:4

RESERVED1

RESERVED

RO

0x0

ErrticErr

Erratic Error (ErrticErr)
The core sets this bit to report any erratic errors
(phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted For at
least 2 ms, due to PHY error) seen on the UTMI+ .
Because of erratic errors, DWC_otg goes into Suspended
state and an interrupt is generated to the application with Early
Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
If the early suspend is asserted due to an erratic error, the
application can only perform a soft disconnect recover.

Value	Description
0x0	No Erratic Error
0x1	Erratic Error

RO

0x0

2:1

EnumSpd

Enumerated Speed (EnumSpd)
Indicates the speed at which the DWC_otg core has come up
after speed detection through a chirp sequence.
 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
 2'b10: Low speed (PHY clock is running at 6 MHz)
 2'b11: Full speed (PHY clock is running at 48 MHz)
Low speed is not supported For devices using a UTMI+ PHY.

Value	Description
0x0	High speed (PHY clock is running at 30 or 60 MHz)
0x1	Full speed (PHY clock is running at 30 or 60 MHz)
0x2	Low speed (PHY clock is running at 6 MHz)
0x3	Full speed (PHY clock is running at 48 MHz)

RO

0x1

SuspSts

Suspend Status (SuspSts)
In Device mode, this bit is Set as long as a Suspend condition is
detected on the USB. The core enters the Suspended state
when there is no activity on the phy_line_state_i signal For an
extended period of time. The core comes out of the suspend:
 When there is any activity on the phy_line_state_i signal
 When the application writes to the Remote Wakeup Signaling
bit in the Device Control register (DCTL.RmtWkUpSig).

Value	Description
0x0	No suspend state
0x1	Suspend state

RO

0x0