priv 

         This register controls access to various Peripherals depending on the privilege setting. By default, all slaves will be assumed as Privileged. To allow non-Privileged access to a slave, the corresponding bit for the slave must be set. Once set, both Privilege and non-Privileged transactions are allowed to the Slave. Note that the privilege filter only checks for transaction Privilege level, transaction Security is left to Firewalls. Firewalls therefore may still block transaction to Peripherals depending on Security configurations.
Module Instance Base Address Register Address
noc_fw_priv_MemoryMap_priv 0xFFD24800 0xFFD24800

Size: 32

Offset: 0x0

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

tcu

RW 0x0

soc2fpga

RW 0x0

lwsoc2fpga

RW 0x0

uart1

RW 0x0

uart0

RW 0x0

sp_timer1

RW 0x0

sp_timer0

RW 0x0

i2c4

RW 0x0

i2c3

RW 0x0

i2c2

RW 0x0

i2c1

RW 0x0

i2c0

RW 0x0

Reserved

gpio1

RW 0x0

gpio0

RW 0x0

sdmmc

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

emac2

RW 0x0

emac1

RW 0x0

emac0

RW 0x0

spi_slave1

RW 0x0

spi_slave0

RW 0x0

spi_master1

RW 0x0

spi_master0

RW 0x0

dma_secure

RW 0x0

dma_nonsecure

RW 0x0

usb1_register

RW 0x0

usb0_register

RW 0x0

Reserved

nand_data

RW 0x0

nand_register

RW 0x0

priv Fields

Bit Name Description Access Reset
31 tcu 
Privilege bit for TCU slave. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
30 soc2fpga 
Privilege bit for SOC2FPGA. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
29 lwsoc2fpga 
Privilege bit for Lightweight SOC2FPGA. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
28 uart1 
Privilege bit for uart1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
27 uart0 
Privilege bit for uart0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
26 sp_timer1 
Privilege bit for sp_timer1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
25 sp_timer0 
Privilege bit for sp_timer0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
24 i2c4 
Privilege bit for i2c4. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
23 i2c3 
Privilege bit for i2c3. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
22 i2c2 
Privilege bit for i2c2. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
21 i2c1 
Privilege bit for i2c1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
20 i2c0 
Privilege bit for i2c0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
18 gpio1 
Privilege bit for gpio1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
17 gpio0 
Privilege bit for gpio0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
16 sdmmc 
Privilege bit for sdmmc. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
13 emac2 
Privilege bit for emac2. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
12 emac1 
Privilege bit for emac1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
11 emac0 
Privilege bit for emac0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
10 spi_slave1 
Privilege bit for spi_slave1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
9 spi_slave0 
Privilege bit for spi_slave0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
8 spi_master1 
Privilege bit for spi_master1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
7 spi_master0 
Privilege bit for spi_master0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
6 dma_secure 
Privilege bit for dma_secure. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
5 dma_nonsecure 
Privilege bit for dma_nonsecure. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
4 usb1_register 
Privilege bit for usb1_register. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
3 usb0_register 
Privilege bit for usb0_register. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
1 nand_data 
Privilege bit for nand_data. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0
0 nand_register 
Privilege bit for nand register. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave
 RW 0x0