IC_RXFLR

         Name: I2C Receive FIFO Level Register
Size: RX_ABW + 1
Address Offset: 0x78
Read/Write Access: Read
This register contains the number of valid data
entries in the receive FIFO buffer. It is cleared
whenever:
- The I2C is disabled
- Whenever there is a transmit abort caused by any
  of the events tracked in IC_TX_ABRT_SOURCE
The register increments whenever data is placed into
the receive FIFO and decrements when data is
taken from the receive FIFO.

Module Instance	Base Address	Register Address
`i_i2c_emac_0_DW_apb_i2c_addr_block1`	`0xFFC02A00`	`0xFFC02A78`
`i_i2c_emac_1_DW_apb_i2c_addr_block1`	`0xFFC02B00`	`0xFFC02B78`
`i_i2c_emac_2_DW_apb_i2c_addr_block1`	`0xFFC02C00`	`0xFFC02C78`

Size: 32

Offset: 0x78

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_RXFLR` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_RXFLR` `RO 0x0`									`RXFLR` `RO 0x0`

IC_RXFLR Fields

Bit	Name	Description	Access	Reset
31:7	`RSVD_RXFLR`	Reserved bits - Read Only	`RO`	`0x0`
6:0	`RXFLR`	Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0	`RO`	`0x0`