reg_pipeline0
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010130

Size: 32

Offset: 0x130

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_cmd_fifo_pipeline_en

RW 0x0

cfg_ac_tile_reg_ena

RW 0x0

cfg_ctl2dbc_tile_reg_ena

RW 0x0

Reserved

cfg_ctl2dbc_reg_ena

RW 0x0

cfg_rb_ptr_reg_ena

RW 0x0

cfg_wb_ptr_reg_ena

RW 0x0

cfg_arbiter_reg_ena

RW 0x0

reg_pipeline0 Fields

Bit Name Description Access Reset
7 cfg_cmd_fifo_pipeline_en 
iohmc_ctrl_mmr_top_inst.cfg_cmd_fifo_reserve_en
Name:Avalon Almost-Ready Enable
Description:Enables Almost-Ready behavior in input command FIFO.
RW 0x0
6 cfg_ac_tile_reg_ena 
iohmc_ctrl_mmr_top_inst.cfg_ac_tile_reg_ena
Name:AC Pipe Stage Enable (Tile)
Description:Set to 1 to enable address/command tile pipe stage.
Set to 0 to disable address/command tile pipe stage.
RW 0x0
5 cfg_ctl2dbc_tile_reg_ena 
iohmc_ctrl_mmr_top_inst.cfg_ctl2dbc_tile_reg_ena
Name:Reserved
Description:TBD
RW 0x0
3 cfg_ctl2dbc_reg_ena 
iohmc_ctrl_mmr_top_inst.cfg_ctl2dbc_reg_ena
Name:Reserved
Description:TBD
RW 0x0
2 cfg_rb_ptr_reg_ena 
iohmc_ctrl_mmr_top_inst.cfg_rb_ptr_reg_ena
Name:Bypass Read Buffer (RB) Retire Pointer
Description:1’b0 – Live RB Retire Pointer path (Default)
1’b0 – Flop RB Retire Pointer path
RW 0x0
1 cfg_wb_ptr_reg_ena 
iohmc_ctrl_mmr_top_inst.cfg_wb_ptr_reg_ena
Name:Bypass Write Buffer (WB) Retire Pointer
Description:1’b0 – Live WB Retire Pointer path (Default)
1’b1 – Flop WB Retire Pointer path
RW 0x0
0 cfg_arbiter_reg_ena 
iohmc_ctrl_mmr_top_inst.cfg_arbiter_reg_ena
Name:Reserved
Description:TBD
RW 0x0