reg_sideband14
Sideband 14 Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst | 0xF8010000 | 0xF80100E4 |
Size: 32
Offset: 0xE4
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
mmr_refresh_bank RW 0x0 |
|||||||||||||||
reg_sideband14 Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15:0 | mmr_refresh_bank |
iohmc_ctrl_mmr_top_inst.mmr_refresh_bank[15:0] Name:LPDDR3 Per Bank Refresh Description:When asserted, indictates LPDDR3 per bank Refresh. When not asserted, indicates LPDDR3 all bank refresh. |
RW | 0x0 |