GIC_VCPUifHyp Summary

Memory map for the GIC virtual CPU interface control registers. Contains all registers with the GICH prefix. Note: This provides access to the control registers for the current CPU. It is expected that this block will only be made accessible to the hypervisor. For details of these registers, please refer to the Arm https://developer.arm.com/docs/ddi0471/b Corelink GIC-400 Generic Interrupt Controller Technical Reference Manual.

Base Address: 0xFFFC4000

Register

Address Offset

 Bit Fields
i_gic_wrapper_VCPUifHyp

GICH_HCR

0x0

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_VTR

0x4

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_VMCR

0x8

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_MISR

0x10

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_EISR0

0x20

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_ELSR0

0x30

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_APR0

0xF0

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_LR0

0x100

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_LR1

0x104

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_LR2

0x108

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

GICH_LR3

0x10C

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved