GHWCFG4
User HW Config4 Register
Module Instance | Base Address | Register Address |
---|---|---|
i_usbotg_0_DWC_otg_intreg | 0xFFB00000 | 0xFFB00050 |
i_usbotg_1_DWC_otg_intreg | 0xFFB40000 | 0xFFB40050 |
Size: 32
Offset: 0x50
Access: RO
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DescDMA RO 0x1 |
DescDMAEnabled RO 0x1 |
INEps RO 0xF |
DedFifoMode RO 0x1 |
SessEndFltr RO 0x0 |
BValidFltr RO 0x0 |
AValidFltr RO 0x0 |
VBusValidFltr RO 0x0 |
IddgFltr RO 0x0 |
NumCtlEps RO 0xF |
||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PhyDataWidth RO 0x0 |
RESERVED RO 0x0 |
ExtendedHibernation RO 0x0 |
Hibernation RO 0x0 |
AhbFreq RO 0x1 |
PartialPwrDn RO 0x0 |
NumDevPerioEps RO 0x0 |
GHWCFG4 Fields
Bit | Name | Description | Access | Reset | ||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | DescDMA |
Scatter/Gather DMA configuration 1'b0: Non Dynamic configuration 1'b1: Dynamic configuration
|
RO | 0x1 | ||||||||||||||||||||||||||||||||||
30 | DescDMAEnabled |
Scatter/Gather DMA configuration 1'b0: Non-Scatter/Gather DMA configuration 1'b1: Scatter/Gather DMA configuration
|
RO | 0x1 | ||||||||||||||||||||||||||||||||||
29:26 | INEps |
Number of Device Mode IN Endpoints Including Control Endpoints (INEps) Range 0 -15 0 : 1 IN Endpoint 1 : 2 IN Endpoints .... 15 : 16 IN Endpoints
|
RO | 0xF | ||||||||||||||||||||||||||||||||||
25 | DedFifoMode |
Enable Dedicated Transmit FIFO For device IN Endpoints (DedFifoMode) 1'b0 : Dedicated Transmit FIFO Operation not enabled. 1'b1 : Dedicated Transmit FIFO Operation enabled.
|
RO | 0x1 | ||||||||||||||||||||||||||||||||||
24 | SessEndFltr |
session_end Filter Enabled (SessEndFltr) 1'b0: No filter 1'b1: Filter
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
23 | BValidFltr |
b_valid Filter Enabled (BValidFltr) 1'b0: No filter 1'b1: Filter
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
22 | AValidFltr |
a_valid Filter Enabled (AValidFltr) 1'b0: No filter 1'b1: Filter
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
21 | VBusValidFltr |
VBUS Valid Filter Enabled (VBusValidFltr) 1'b0: No filter 1'b1: Filter
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
20 | IddgFltr |
IDDIG Filter Enable (IddgFltr) 1'b0: No filter 1'b1: Filter
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
19:16 | NumCtlEps |
Number of Device Mode Control Endpoints in Addition to Endpoint 0 (NumCtlEps) Range: 0-15
|
RO | 0xF | ||||||||||||||||||||||||||||||||||
15:14 | PhyDataWidth |
UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width (PhyDataWidth) When a ULPI PHY is used, an internal wrapper converts ULPI to UTMI+ . 2'b00: 8 bits 2'b01: 16 bits 2'b10: 8/16 bits, software selectable Others: Reserved
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
13:8 | RESERVED |
RESERVED |
RO | 0x0 | ||||||||||||||||||||||||||||||||||
7 | ExtendedHibernation |
Enable Hibernation 1'b0: Extended Hibernation feature not enabled 1'b1: Extended Hibernation feature enabled
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
6 | Hibernation |
Enable Hibernation (Hibernation) 1'b0: Hibernation feature not enabled 1'b1: Hibernation feature enabled
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
5 | AhbFreq |
Minimum AHB Frequency Less Than 60 MHz (AhbFreq) 1'b0: No 1'b1: Yes
|
RO | 0x1 | ||||||||||||||||||||||||||||||||||
4 | PartialPwrDn |
Enable Partial Power Down (PartialPwrDn) 1'b0: Partial Power Down Not Enabled 1'b1: Partial Power Down Enabled
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||
3:0 | NumDevPerioEps |
Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) Range: 0-15 |
RO | 0x0 |