IC_TAR 

         Name: I2C Target Address Register
Size: 12 bits; when I2C_DYNAMIC_TAR_UPDATE = 0 and IC_DEVICE_ID = 0
      13 bits; when I2C_DYNAMIC_TAR_UPDATE = 1 and IC_DEVICE_ID = 0
      14 bits; when IC_DEVICE_ID=1 irrespective of I2C_DYNAMIC_TAR_UPDATE is set.
      17 bits; when IC_SMBUS=1
Address Offset: 0x04
Read/Write Access: Read/Write
If the configuration parameter I2C_DYNAMIC_TAR_UPDATE is set to 'No' (0),
this register is 12 bits wide, and bits 31:12 are reserved. This register
can be written to only when IC_ENABLE[0] is set to 0.
However, if I2C_DYNAMIC_TAR_UPDATE = 1, then the register becomes 13 bits wide.
All bits can be dynamically updated as long as any set of the following
conditions are true:
- DW_apb_i2c is NOT enabled (IC_ENABLE[0] is set to 0);
   or
- DW_apb_i2c is enabled (IC_ENABLE[0]=1);
   AND
  DW_apb_i2c is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0);
   AND
  DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1);
   AND
  there are NO entries in the TX FIFO (IC_STATUS[2]=1)
Module Instance Base Address Register Address
sdm_i_i2c_0_DW_apb_i2c_addr_block1 0xFF8D0100 0xFF8D0104
sdm_i_i2c_1_DW_apb_i2c_addr_block1 0xFF8D0200 0xFF8D0204

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_TAR_2

RO 0x0

RSVD_SMBUS_QUICK_CMD

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_TAR_1

RO 0x0

RSVD_DEVICE_ID

RO 0x0

IC_10BITADDR_MASTER

RW 0x1

SPECIAL

RW 0x0

GC_OR_START

RW 0x0

IC_TAR

RW 0x55

IC_TAR Fields

Bit Name Description Access Reset
31:17 RSVD_IC_TAR_2 
Reserved bits - Read Only
 RO 0x0
16 RSVD_SMBUS_QUICK_CMD 
Reserved bits - Read Only
 RO 0x0
15:14 RSVD_IC_TAR_1 
Reserved bits - Read Only
 RO 0x0
13 RSVD_DEVICE_ID 
Reserved bits - Read Only
 RO 0x0
12 IC_10BITADDR_MASTER 
This bit controls whether the DW_apb_i2c starts its transfers in 7-
or 10-bit addressing mode when acting as a master.
0: 7-bit addressing
1: 10-bit addressing
Dependencies: This bit exists in this register only if the
I2C_DYNAMIC_TAR_UPDATE configuration parameter is set
to 'Yes' (1).
Reset value: IC_10BITADDR_MASTER configuration
parameter
Value Description
0x0 Address 7Bit transmission format
0x1 Address 10Bit transmission format
RW 0x1
11 SPECIAL 
This bit indicates whether software performs a Device-ID or General Call or
START BYTE command.
0: ignore bit 10 GC_OR_START and use IC_TAR normally
1: perform special I2C command as specified in Device_ID or GC_OR_START
   bit
Reset value: 0x0
Value Description
0x0 Disables programming of GENERAL_CALL or START_BYTE transmission
0x1 Enables programming of GENERAL_CALL or START_BYTE transmission
RW 0x0
10 GC_OR_START 
If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a
General Call or START byte command is to be performed by the
DW_apb_i2c.
0: General Call Address  after issuing a General Call, only writes
   may be performed. Attempting to issue a read command results in
   setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.
   The DW_apb_i2c remains in General Call mode until the
   SPECIAL bit value (bit 11) is cleared.
1: START BYTE
Reset value: 0x0
Value Description
0x0 GENERAL_CALL byte transmission
0x1 START byte transmission
RW 0x0
9:0 IC_TAR 
This is the target address for any master transaction. When
transmitting a General Call, these bits are ignored. To generate a
START BYTE, the CPU needs to write only once into these bits.
Reset value: IC_DEFAULT_TAR_SLAVE_ADDR configuration
parameter
If the IC_TAR and IC_SAR are the same, loopback exists but the
FIFOs are shared between master and slave, so full loopback is
not feasible. Only one direction loopback mode is supported
(simplex), not duplex. A master cannot transmit to itself; it can
transmit to only a slave.
 RW 0x55