GRSTCTL

Mode:Host and Device
AHB Master Idle (AHBIdle)
Indicates that the AHB Master State Machine is in the IDLE
condition.

Mode:Host and Device
DMA Request Signal (DMAReq)
Indicates that the DMA request is in progress. Used For debug.

RESERVED

Mode:Host and Device
TxFIFO Number (TxFNum)
This is the FIFO number that must be flushed using the TxFIFO
Flush bit. This field must not be changed until the core clears the
TxFIFO Flush bit.
 5'h0:
- Non-periodic TxFIFO flush in Host mode
- Non-periodic TxFIFO flush in device mode when in shared
FIFO operation
- Tx FIFO 0 flush in device mode when in dedicated FIFO
mode
 5'h1:
- Periodic TxFIFO flush in Host mode
- Periodic TxFIFO 1 flush in Device mode when in shared
FIFO operation
- TXFIFO 1 flush in device mode when in dedicated FIFO
mode
 5'h2:
- Periodic TxFIFO 2 flush in Device mode when in shared
FIFO operation
- TXFIFO 2 flush in device mode when in dedicated FIFO
mode
...
 5'hF:
- Periodic TxFIFO 15 flush in Device mode when in shared
FIFO operation
- TXFIFO 15 flush in device mode when in dedicated FIFO
mode
 5'h10: Flush all the transmit FIFOs in device or host mode.

Mode:Host and Device
TxFIFO Flush (TxFFlsh)
This bit selectively flushes a single or all transmit FIFOs, but
cannot do so If the core is in the midst of a transaction.
The application must write this bit only after checking that the
core is neither writing to the TxFIFO nor reading from the
TxFIFO. Verify using these registers:
 ReadNAK Effective Interrupt ensures the core is not
reading from the FIFO
 WriteGRSTCTL.AHBIdle ensures the core is not writing
anything to the FIFO.
Flushing is normally recommended when FIFOs are
reconfigured or when switching between Shared FIFO and
Dedicated Transmit FIFO operation. FIFO flushing is also
recommended during device endpoint disable.
The application must wait until the core clears this bit before
performing any operations. This bit takes eight clocks to clear,
using the slower clock of phy_clk or hclk.

Mode:Host and Device
RxFIFO Flush (RxFFlsh)
The application can flush the entire RxFIFO using this bit, but
must first ensure that the core is not in the middle of a
transaction.
The application must only write to this bit after checking that the
core is neither reading from the RxFIFO nor writing to the
RxFIFO.
The application must wait until the bit is cleared before
performing any other operations. This bit requires 8 clocks
(slowest of PHY or AHB clock) to clear.

Mode:Host only
Host Frame Counter Reset (FrmCntrRst)
The application writes this bit to reset the (micro)frame number
counter inside the core. When the (micro)frame counter is reset,
the subsequent SOF sent out by the core has a (micro)frame
number of 0.When application writes 1 to the bit, it might not
be able to read back the value as it will get cleared by the core in a few clock cycles.

Mode:Host and Device
PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)
Resets the PIU FS Dedicated Controller
 All module state machines in FS Dedicated Controller of PIU are
reset to the IDLE state. Used to reset the FS Dedicated controller in PIU in case of any PHY Errors like Loss of activity or Babble Error resulting in the PHY remaining in RX state for more than one frame boundary

Mode:Host and Device
Core Soft Reset (CSftRst)
Resets the hclk and phy_clock domains as follows:
 Clears the interrupts and all the CSR registers except the
following register bits:
- PCGCCTL.RstPdwnModule
- PCGCCTL.GateHclk
- PCGCCTL.PwrClmp
- PCGCCTL.StopPPhyLPwrClkSelclk
- GUSBCFG.PhyLPwrClkSel
- GUSBCFG.DDRSel
- GUSBCFG.PHYSel
- GUSBCFG.FSIntf
- GUSBCFG.ULPI_UTMI_Sel
- GUSBCFG.PHYIf
- GUSBCFG.TxEndDelay
- GUSBCFG.TermSelDLPulse
- GUSBCFG.ULPIClkSusM
- GUSBCFG.ULPIAutoRes
- GUSBCFG.ULPIFsLs
- GGPIO
- GPWRDN
- GADPCTL
- HCFG.FSLSPclkSel
- DCFG.DevSpd
- DCTL.SftDiscon
- All module state machines
 All module state machines (except the AHB Slave Unit) are
reset to the IDLE state, and all the transmit FIFOs and the
receive FIFO are flushed.
 Any transactions on the AHB Master are terminated as soon
as possible, after gracefully completing the last data phase of
an AHB transfer. Any transactions on the USB are terminated
immediately.
 When Hibernation or ADP feature is enabled, the PMU module is not
reset by the Core Soft Reset.
The application can write to this bit any time it wants to reset the
core. This is a self-clearing bit and the core clears this bit after
all the necessary logic is reset in the core, which can take
several clocks, depending on the current state of the core. Once
this bit is cleared software must wait at least 3 PHY clocks
before doing any access to the PHY domain (synchronization
delay). Software must also must check that bit 31 of this register
is 1 (AHB Master is IDLE) before starting any operation.
Typically software reset is used during software development
and also when you dynamically change the PHY selection bits in
the USB configuration registers listed above. When you change
the PHY, the corresponding clock For the PHY is selected and
used in the PHY domain. Once a new clock is selected, the PHY
domain has to be reset for proper operation.