CAIUTTR

         CAIU Transaction Throttle Register

Module Instance	Base Address	Register Address
`CCU_cpu0`	`0xF7000000`	`0xF7000008`

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`TransThrottleEn` `RW 0x0`	`TransThrottleMask` `RW 0x0`	`rsvd2` `RO 0x0`						`TransDelta` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`rsvd1` `RO 0x0`								`TransLimit` `RW 0x0`

CAIUTTR Fields

Bit	Name	Description	Access	Reset
31	`TransThrottleEn`	Transaction table throttle feature enable	`RW`	`0x0`
30	`TransThrottleMask`	Transaction table throttle input mask	`RW`	`0x0`
29:24	`rsvd2`	Reserved (RAZ/WI)	`RO`	`0x0`
23:16	`TransDelta`	Transaction table delta	`RW`	`0x0`
15:8	`rsvd1`	Reserved (RAZ/WI)	`RO`	`0x0`
7:0	`TransLimit`	Transaction table limit	`RW`	`0x0`