MSTICR

         Multi-Master Interrupt Clear Register

Module Instance	Base Address	Register Address
`i_spis_0_ssi_address_block`	`0xFFDA2000`	`0xFFDA2044`
`i_spis_1_ssi_address_block`	`0xFFDA3000`	`0xFFDA3044`

Size: 32

Offset: 0x44

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_MSTICR` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_MSTICR` `RO 0x0`															`MSTICR` `RO 0x0`

MSTICR Fields

Bit	Name	Description	Access	Reset
31:1	`RSVD_MSTICR`	Reserved bits - Read Only	`RO`	`0x0`
0	`MSTICR`	Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_mst_intr interrupt; writing has no effect.	`RO`	`0x0`

Bit

Name

Description

Access

Reset

31:1

RSVD_MSTICR

Reserved bits - Read Only

RO

0x0

MSTICR

Clear Multi-Master Contention Interrupt.
This register reflects the status of the interrupt. A read from this
register clears the ssi_mst_intr interrupt; writing has no effect.

RO

0x0