ecc_correction 

         Correction capability required and the Erase threshold value.
Module Instance Base Address Register Address
sdm_i_nand_config 0xFFA10000 0xFFA101B0

Size: 32

Offset: 0x1B0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

erase_threshold

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

value

RW 0x8

ecc_correction Fields

Bit Name Description Access Reset
31:16 erase_threshold 
This value informs the ECC logic of the number of 0's to count
                                          in a page before considering it as Erased. If the number of 0's in 
                                          the page being read is less than the value in this register, 
                                          an erased page is inferred and no un-correctable error will be flagged 
                                          for that page. If ECC is disabled, the erased_page interrupt shall be 
                                          set as explained above. If ECC is enabled, in addition to the above 
                                          condition, only when the ECC logic detects an un-correctable error for 
                                          that page will the erased_page interrupt be flagged. If the ECC logic 
                                          detects a no-error or correctable error page, this erased page interrupt 
                                          will not be set. A value of ZERO in this register will disabled checking for
                                          erased pages. Erased page detection logic will be activated only in MAIN or 
                                          MAIN+SPARE or META-DATA(if available) modes of operation.
 RW 0x0
7:0 value 
The required correction capability. A smaller correction capability will 
                                 lead to lesser number of ECC check-bits being written per ECC sector.
                                 The supported ECC correction levels are -
                                 [list]
                                  [*] 16,8,4 over 512 bytes.
                                  
                                    [*] 24 over 1024 bytes.
                                  
                                  [*] All other values will cause the correction value in the controller
                                      to fall back to the previously selected value.
                                 [/list]
 RW 0x8