CTRLR0
Control Register 0:
This register controls the serial data transfer. It is impossible to
write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi
is enabled and disabled by writing to the SSIENR register.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_spis_0_ssi_address_block | 0xFFDA2000 | 0xFFDA2000 |
| i_spis_1_ssi_address_block | 0xFFDA3000 | 0xFFDA3000 |
Size: 32
Offset: 0x0
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
RSVD_CTRLR0 RO 0x0 |
SPI_FRF RO 0x0 |
DFS_32 RW 0x7 |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CFS RW 0x0 |
SRL RW 0x0 |
SLV_OE RW 0x0 |
TMOD RW 0x0 |
SCPOL RW 0x0 |
SCPH RW 0x0 |
FRF RW 0x0 |
DFS RO 0x0 |
||||||||
CTRLR0 Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31:23 | RSVD_CTRLR0 |
Reserved bits - Read Only |
RO | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22:21 | SPI_FRF |
SPI Frame Format: Selects data frame format for Transmitting/Receiving the data 00 - Standard SPI Format 01 - Dual SPI Format 10 - Quad SPI Format Bits only valid when SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode. |
RO | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20:16 | DFS_32 |
Data Frame Size in 32-bit transfer size mode. Selects the data frame length. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data Note: When SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode and SPI_FRF is not set to 2’b00. DFS value should be multiple of 2 if SPI_FRF = 01, and DFS value should be multiple of 4 if SPI_FRF = 10.
|
RW | 0x7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15:12 | CFS |
Control Frame Size. Selects the length of the control word for the Microwire frame format When SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode and SPI_FRF is not set to 2’b00. This bit defines Length of Address to be transmitted. Refer Table 4 6 for field decode. Only after this much bits are programmed in to the FIFO the transfer can begin.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | SRL |
Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. 0 - Normal Mode Operation 1 - Test Mode Operation
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | SLV_OE |
Slave Output Enable. Relevant only when the DW_apb_ssi is configured as a serial-slave device. When configured as a serial master, this bit field has no functionality. This bit enables or disables the setting of the ssi_oe_n output from the DW_apb_ssi serial slave. When SLV_OE = 1, the ssi_oe_n output can never be active. When the ssi_oe_n output controls the tri-state buffer on the txd output from the slave, a high impedance state is always present on the slave txd output when SLV_OE = 1. This is useful when the master transmits in broadcast mode (master transmits data to all slave devices). Only one slave may respond with data on the master rxd line. This bit is enabled after reset and must be disabled by software (when broadcast mode is used), if you do not want this device to respond with data. 0 - Slave txd is enabled 1 - Slave txd is disabled
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9:8 | TMOD |
Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. 00 - Transmit & Receive 01 - Transmit Only 10 - Receive Only 11 - EEPROM Read When SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode and SPI_FRF is not set to 2’b00. There are only two valid combinations: 01 Read 10 - Write
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | SCPOL |
Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the DW_apb_ssi master is not actively transferring data on the serial bus. 0 - Inactive state of serial clock is low 1 - Inactive state of serial clock is high
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | SCPH |
Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 0: Serial clock toggles in middle of first data bit 1: Serial clock toggles at start of first data bit
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5:4 | FRF |
Frame Format. Selects which serial protocol transfers the data. 00 - Motorola SPI 01 - Texas Instruments SSP 10 - National Semiconductors Microwire 11 - Reserved
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3:0 | DFS |
Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is configured to 16. If SSI_MAX_XFER_SIZE is configured to 32, then writing to this field will not have any effect. Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data Note: When SSI_SPI_MODE is either set to “Dual” or “Dual/Quad Both” mode and SPI_FRF is not set to 2’b00. DFS value should be multiple of 2 if SPI_FRF = 01, and DFS value should be multiple of 4 if SPI_FRF = 10.
|
RO | 0x0 |