reg_sideband16
| Module Instance | Base Address | Register Address |
|---|---|---|
| iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst | 0xF8010000 | 0xF801013C |
Size: 32
Offset: 0x13C
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
mmr_3ds_refresh_ack RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
mmr_3ds_refresh_ack RO 0x0 |
|||||||||||||||
reg_sideband16 Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:0 | mmr_3ds_refresh_ack |
iohmc_ctrl_mmr_top_inst.mmr_3ds_refresh_ack[31:0] Name:3DS Refresh Acknowledge Description:Acknowledge to indicate 3DS refresh is done. Bit0: PR0, LR0 Bit1: PR0, LR1 Bit2: PR0, LR2 Bit3: PR0, LR3 Bits4-7: Reserved Bit8: PR1, LR0 Bit9: PR1, LR1 Bit10: PR1, LR2 Bit11: PR1, LR3 Bits12-15: Reserved Bit16: PR2, LR0 Bit17: PR2, LR1 Bit18: PR2, LR2 Bit19: PR2, LR3 Bits20-23: Reserved Bit24: PR3, LR0 Bit25: PR3, LR1 Bit26: PR3, LR2 Bit27: PR3, LR3 Bits 28-32: Reserved Note1: PR=Physical Rank Note2: LR=Logical Rank |
RO | 0x0 |