hdskreq 

         This register includes fields for software to initiate the handshake with certain peripherals. Software must clear the request bit except for "debug_l3noc_req" once it sees the corresponding acknowledge bit has been set in the hdskack register. "debug_l3noc_req" is cleared by hardware once the corresponding dbg_rst or csdap_rst is/are asserted. Software should implement its own timeout.
Fields are reset by a cold reset. It is recommended that software should clear this bit on every warm reset.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD11014

Size: 32

Offset: 0x14

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

debug_l3noc_req

RW 0x0

l3noc_dbg_req

RW 0x0

etrstallreq

RW 0x0

fpgahsreq

RW 0x0

Reserved

mpfe_hmca_drainreq

RW 0x0

hdskreq Fields

Bit Name Description Access Reset
5 debug_l3noc_req 
Software writes this field 1 to initiate a handshake request to L3 NOC. This handshake is done to stop L3NOC accept any new transactions and allow all outstanding transactions to drain. 
Hardware clears the request bit when dbg_rst or csdap_rst or both are asserted by SW by writing to the dbgmodrst register. Note that it is possible for the L3NOC to never assert DEBUG_L3NOC_ACK so software should timeout in this case.
 RW 0x0
4 l3noc_dbg_req 
Software writes this field 1 to initiate a handshake request to L3 NOC. This handshake is done to stop L3NOC accept any new transactions and allow all outstanding transactions to drain. Software waits for the L3NOC_DBG_ACK to be active and then writes this field to 0. Note that it is possible for the L3NOC to never assert L3NOC_DBG_ACK so software should timeout in this case.
 RW 0x0
3 etrstallreq 
Software sets bit field to 1 to ask the ETR to that stall its AXI master to the L3 Interconnect.
Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. Note that it is possible for the ETR to never assert ETRSTALLACK so software should timeout if ETRSTALLACK is never asserted.
 RW 0x0
2 fpgahsreq 
Software writes this field 1 to initiate a handshake request to FPGA. Software waits for the FPGAHSACK to be active and then writes this field to 0. Note that it is possible for the FPGA to never assert FPGAHSACK so software should timeout in this case.
 RW 0x0
0 mpfe_hmca_drainreq 
Software writes this field 1 to request that the SDRAM Controller Subsystem to stop accepting any new transactions and allows all outstanding transactions to drain. 
Software waits for the MPFE_HMCA_DRAINACK to be 1 and then writes this field to 0.  Note that it is possible for the SDRAM Controller Subsystem to never assert MPFE_HMCA_DRAINACK so software should timeout if MPFE_HMCA_DRAINACK is never asserted.
 RW 0x0