IER
Interrupt Enable Register:
Interrupt Enable Register, when the DLAB bit is zero; Divisor Latch (High), when the DLAB bit is one.
Each of the bits used has a different function and will be detailed in the bit
field descriptions.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_uart_0_uart_address_block | 0xFFC02000 | 0xFFC02004 |
| i_uart_1_uart_address_block | 0xFFC02100 | 0xFFC02104 |
Size: 32
Offset: 0x4
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
RSVD_IER_31to8 RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RSVD_IER_31to8 RO 0x0 |
PTIME RW 0x0 |
RSVD_IER_6to4 RO 0x0 |
EDSSI RW 0x0 |
ELSI RW 0x0 |
ETBEI RW 0x0 |
ERBFI RW 0x0 |
|||||||||
IER Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:8 | RSVD_IER_31to8 |
Reserved bits [31:8] - Read Only |
RO | 0x0 | ||||||
| 7 | PTIME |
Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. Writeable only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled
|
RW | 0x0 | ||||||
| 6:4 | RSVD_IER_6to4 |
Reserved bits [6:4] - Read Only |
RO | 0x0 | ||||||
| 3 | EDSSI |
Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled
|
RW | 0x0 | ||||||
| 2 | ELSI |
Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled
|
RW | 0x0 | ||||||
| 1 | ETBEI |
Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled
|
RW | 0x0 | ||||||
| 0 | ERBFI |
Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled
|
RW | 0x0 |