reg_ctrlcfg1 

         Control Configuration 1 Register
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF801002C

Size: 32

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_dbc3_enable_dm

RW 0x0

cfg_dbc2_enable_dm

RW 0x0

cfg_dbc1_enable_dm

RW 0x0

cfg_dbc0_enable_dm

RW 0x0

cfg_ctrl_enable_dm

RW 0x0

cfg_dqstrk_en

RW 0x0

cfg_reserve3

RW 0x0

cfg_reorder_read

RW 0x0

cfg_dbc3_reorder_rdata

RW 0x0

cfg_dbc2_reorder_rdata

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc1_reorder_rdata

RW 0x0

cfg_dbc0_reorder_rdata

RW 0x0

cfg_ctrl_reorder_rdata

RW 0x0

cfg_reorder_data

RW 0x0

cfg_dbc3_enable_ecc

RW 0x0

cfg_dbc2_enable_ecc

RW 0x0

cfg_dbc1_enable_ecc

RW 0x0

cfg_dbc0_enable_ecc

RW 0x0

cfg_ctrl_enable_ecc

RW 0x0

cfg_addr_order

RW 0x0

cfg_dbc3_burst_length

RW 0x0

reg_ctrlcfg1 Fields

Bit Name Description Access Reset
30 cfg_dbc3_enable_dm 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.
RW 0x0
29 cfg_dbc2_enable_dm 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.
RW 0x0
28 cfg_dbc1_enable_dm 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.
RW 0x0
27 cfg_dbc0_enable_dm 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.
RW 0x0
26 cfg_ctrl_enable_dm 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_enable_dm
Name:DM Pins Present
Description:Set to a one to enable DRAM operation if DM pins are connected.
RW 0x0
25 cfg_dqstrk_en 
iohmc_ctrl_mmr_top_inst.cfg_dqstrk_en
Name:DQS Tracking Enable
Description:Enables DQS tracking in the PHY.
1’b1 – Enable Long/Short DQS Tracking
Post-REFRESH-EXIT – Refer to cfg_short_dqstrk_ctrl_en
Post-SELFREFRESH-EXIT – IOPHYSEQ performs Long DQS Tracking
1’b0 – Disable DQS Tracking
RW 0x0
24:19 cfg_reserve3 
iohmc_ctrl_mmr_top_inst.cfg_reserve3[5:0]
Name:Reserved
Description:TBD
 RW 0x0
18 cfg_reorder_read 
iohmc_ctrl_mmr_top_inst.cfg_reorder_read
Name:Read Command Reorder Enable
Description:This bit controls whether the controller can re-order read command to.  1’b0 – Disable, 1’b1 – Enable
RW 0x0
17 cfg_dbc3_reorder_rdata 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_reorder_rdata
Name:DBC3 – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.
RW 0x0
16 cfg_dbc2_reorder_rdata 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_reorder_rdata
Name:DBC2 – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.
RW 0x0
15 cfg_dbc1_reorder_rdata 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_reorder_rdata
Name:DBC1 – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.
RW 0x0
14 cfg_dbc0_reorder_rdata 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_reorder_rdata
Name:DBC0 – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.
RW 0x0
13 cfg_ctrl_reorder_rdata 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_reorder_rdata
Name:CTRL – Read  Data Reorder Enable
Description:This bit controls whether the controller need to re-order the read return data.
RW 0x0
12 cfg_reorder_data 
iohmc_ctrl_mmr_top_inst.cfg_reorder_data
Name:Column Command Reorder Enable
Description:This bit controls whether the controller can re-order operations to optimize SDRAM bandwidth.  It should generally be set to a one.
RW 0x0
11 cfg_dbc3_enable_ecc 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_enable_ecc
Name:DBC3 – ECC Enable
Description:Enable the generation and checking of ECC.
RW 0x0
10 cfg_dbc2_enable_ecc 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_enable_ecc
Name:DBC2 – ECC Enable
Description:Enable the generation and checking of ECC.
RW 0x0
9 cfg_dbc1_enable_ecc 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_enable_ecc
Name:DBC1 – ECC Enable
Description:Enable the generation and checking of ECC.
RW 0x0
8 cfg_dbc0_enable_ecc 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_enable_ecc
Name:DBC0 – ECC Enable
Description:Enable the generation and checking of ECC.
RW 0x0
7 cfg_ctrl_enable_ecc 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_enable_ecc
Name:Ctrl – ECC Enable
Description:Enable the generation and checking of ECC.
RW 0x0
6:5 cfg_addr_order 
iohmc_ctrl_mmr_top_inst.cfg_addr_order[1:0]
Name:Address Interleaving Order
Description:Selects the order for address interleaving.  Programming this field with different values gives different mappings between the AXI or Avalon-MM address and the SDRAM address. Program this field with the following binary values to select the ordering. “00” – chip, row, bank, column; “01” – chip, bank, row, column; “10”-row, chip, bank, column
RW 0x0
4:0 cfg_dbc3_burst_length 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_burst_length[4:0]
Name:DBC3 – DRAM Memory Burst Length
Description:Configures burst length for DBC3.  Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type.  For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary “01000”).
RW 0x0