DOEPTSIZ0

         Device OUT Endpoint 0 Transfer Size Register

Module Instance	Base Address	Register Address
`i_usbotg_0_DWC_otg_intreg`	`0xFFB00000`	`0xFFB00B10`
`i_usbotg_1_DWC_otg_intreg`	`0xFFB40000`	`0xFFB40B10`

Size: 32

Offset: 0xB10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED` `RO 0x0`	`SUPCnt` `RW 0x0`		`RESERVED1` `RO 0x0`									`PktCnt` `RW 0x0`	`RESERVED2` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED2` `RO 0x0`									`XferSize` `RW 0x0`

DOEPTSIZ0 Fields

Bit

Name

Description

Access

Reset

RESERVED

RESERVED

RO

0x0

30:29

SUPCnt

SETUP Packet Count (SUPCnt)
This field specifies the number of back-to-back SETUP data
packets the endpoint can receive.
 2'b01: 1 packet
 2'b10: 2 packets
 2'b11: 3 packets

Value	Description
0x1	1 packet
0x2	2 packets
0x3	3 packets

RW

0x0

28:20

RESERVED1

RESERVED

RO

0x0

PktCnt

Packet Count (PktCnt)
This field is decremented to zero after a packet is written into the
RxFIFO.

RW

0x0

18:7

RESERVED2

RESERVED

RO

0x0

6:0

XferSize

Transfer Size (XferSize)
Indicates the transfer size in bytes For endpoint 0. The core
interrupts the application only after it has exhausted the transfer
size amount of data. The transfer size can be Set to the
maximum packet size of the endpoint, to be interrupted at the
end of each packet.
The core decrements this field every time a packet is read from
the RxFIFO and written to the external memory.

RW

0x0